isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 38

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
Fig 32. HC time domain behavior: example 3.
(frame N)
9.5.2 Control transaction limitations
9.6 Microprocessor loading
9.7 Internal pull-down resistors for downstream ports
In example 3 (see
Frame (SOF) of the next frame has occurred. This will result in undefined behavior for
the ISO data on the USB bus in frame N + 1 (depending on the exact timing data is
corrupted or not). The HC should not raise an AT interrupt in frame N + 1.
The different phases of a control transfer (SETUP, Data and Status) should never be
put in the same ATL.
The maximum amount of data that can be transferred for an endpoint during one
frame is 1023 bytes. The number of USB packets that are needed for this batch of
data depends on the Maximum Packet Size that is specified.
The HCD has to schedule the transactions in a frame. On the other hand, the
microprocessor must have the ability to handle the interrupts coming from HC every
1 ms. It must also be able to do the scheduling for the next frame, reading the frame
information from and writing the next frame information to the buffer RAM in the time
between the end of the current frame and the start of the next frame.
There are four internal 15 k pull-down resistors built in ISP1161 for the two
downstream ports: two resistors for each port. These resistors are software
selectable by programming bit 12 (2_DownstreamPort15Kresistorsel) of the
HcHardwareConfiguration register (20H - read, A0H - write). When bit 12 is cleared
to logic 0, it means that external 15 k pull-down resistors should be used. Bit 12 is
set to logic 1 that indicates the internal built-in 15 k pull-down resistors will be used
instead of external ones (see
This feature is a cost-saving option. However, the power-on reset default value is
logic 0. If you want to use the internal resistors, the HCD must check this bit status
after every reset, because a reset action will clear this bit regardless of it being a
hardware reset or a software reset.
(frame N 1)
Rev. 02 — 13 December 2002
Figure
32), the ISO part is still being written while the Start of
Full-speed USB single-chip host and device controller
Figure
(frame N 2)
33).
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
(frame N 3)
MGT956
ISP1161
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