isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 101

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09567
Product data
13.1.8 Reset device (F6H)
13.2.1 Write/Read Endpoint Buffer (R/W: 10H,12H-1FH/01H–0FH)
13.2 Data flow commands
Table 90:
This command resets the ISP1161 DC in the same way as an external hardware
reset via input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none
Data flow commands are used to manage the data transmission between the USB
endpoints and the system microprocessor. Much of the data flow is initiated via an
interrupt to the microprocessor. The data flow commands are used to access the
endpoints and determine whether the endpoint FIFOs contain valid data.
Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer
receives output data from the host.
This command is used to access endpoint FIFO buffers for reading or writing. First,
the buffer pointer is reset to the beginning of the buffer. Following the command, a
maximum of (M + 1) words can be written or read, with M given by (N
N representing the size of the endpoint buffer. After each read/write action the buffer
pointer is automatically incremented by 2.
In DMA access the first word (the packet length) is skipped: transfers start at the
second word of the endpoint buffer. When reading, the ISP1161 DC can detect the
last word via the End of Packet (EOP) condition. When writing to a bulk/interrupt
endpoint, the endpoint buffer must be completely filled before sending the data to the
host. Exception: when a DMA transfer is stopped by an external EOT condition, the
current buffer content (full or not) is sent to the host.
Remark: Reading data after a Write Endpoint Buffer command or writing data after a
Read Endpoint Buffer command will cause unpredictable behavior of the
ISP1161 DC.
Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)
Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)
Transaction — write/read maximum (M + 1) words (isochronous endpoint: N
bulk/interrupt endpoint: N
The data in the endpoint FIFO must be organized as shown in
of endpoint FIFO access is given
Bit
15 to 0
DcDMACounter register: bit description
Symbol
DMACR[15:0]
Rev. 02 — 13 December 2002
Description
DMA Counter register
Full-speed USB single-chip host and device controller
32)
Table
92.
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Table
ISP1161
91. An example
1)/2 with
101 of 137
1023,