isp1161bm NXP Semiconductors, isp1161bm Datasheet - Page 78

• Manufacturer Part Number: isp1161bm
• Description: Isp1161 Full-speed Universal Serial Bus Single-chip Host And Device Controller
• Manufacturer: NXP Semiconductors

Philips Semiconductors
11. USB device controller (DC)
9397 750 09567
Product data
11.1.1 IN data transfer
11.1.2 OUT data transfer
11.1 DC data transfer operation
The Device Controller (DC) in ISP1161 is based on the Philips ISP1181x Full-Speed
USB Interface Device product family. The functionality and command and register
sets are the same as ISP1181x in the 16-bit bus mode. If there is any difference
found in ISP1181x and ISP1161 datasheet in terms of DC functionality, the ISP1161
datasheet supersedes the content in the ISP1181x datasheet.
In general the DC in ISP1161 provides 16 endpoints for USB device implementation.
Each endpoint can be allocated an amount of RAM space in the on-chip Ping-Pong
buffer RAM.
Remark: the Ping-Pong buffer RAM for the DC is independent of the buffer RAM in
the HC. When the buffer RAM is full, the DC will transfer the data in the buffer RAM to
the USB bus. When the buffer RAM is empty, an interrupt is generated to notify the
microprocessor to feed in the data. The transfer of data between the microprocessor
and the DC can be done in Programmed I/O (PIO) mode or in DMA mode.
The following session explains how the DC of ISP1161 handles an IN data transfer
and an OUT data transfer. In Device mode, ISP1161 acts as a USB device: an IN
data transfer means transfer from ISP1161 to an external USB Host (through the
upstream port) and an OUT transfer means transfer from external USB Host to
ISP1161.
Data transfer procedure:
Data transfer procedure:
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The arrival of the IN token is detected by the SIE by decoding the PID.
The SIE also checks for the device number and endpoint number and verifies
whether they are acceptable.
If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus
register. If the endpoint is full, the contents of the FIFO are sent during the data
phase, otherwise a Not Acknowledge (NAK) handshake is sent.
After the data phase, the SIE expects a handshake (ACK) from the host (except for
ISO endpoints).
On receiving the handshake (ACK), the SIE updates the contents of the
DcEndpointStatus register and the DcInterrupt register, which in turn generates an
interrupt to the microprocessor. For ISO endpoints, the DcInterrupt register is
updated as soon as data is sent because there is no handshake phase.
On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will
know which endpoint has generated the interrupt and reads the contents of the
corresponding DcEndpointStatus register. If the buffer is empty, it fills up the buffer,
so that data can be sent by the SIE at the next IN token phase.
The arrival of the OUT token is detected by the SIE by decoding the PID.
Rev. 02 — 13 December 2002
Full-speed USB single-chip host and device controller
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
ISP1161
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