mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 62

• Manufacturer Part Number: mpc8641
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

High-Speed Serial Interfaces (HSSI)
13.2.2
The DC level requirement for the MPC8641D SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
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The input amplitude requirement
— This requirement is described in detail in the following sections.
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
— For external DC-coupled connection, as described in
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800mV and
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
Clock Receiver
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 40
scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND. Each signal wire of the differential inputs is allowed to swing below and above the
command mode voltage (SGND).
requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 mV and 800 mV peak-peak (from Vmin to Vmax)
with SDn_REF_CLK either left unconnected or tied to ground.
DC Level Requirement for SerDes Reference Clocks
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
shows the SerDes reference clock input requirement for DC-coupled connection
Characteristics,” the maximum average current requirements sets the
Figure 39. Receiver of SerDes Reference Clocks
SD n _REF_CLK
SD n _REF_CLK
Figure 41
50 Ω
50 Ω
shows the SerDes reference clock input
Input
Amp
Section 13.2.1, “SerDes Reference
Freescale Semiconductor