mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 120

• Manufacturer Part Number: mpc8641
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
20.5.1
20.5.1.1
The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:3] and through the
DEVDISR register in software. If a SerDes port is disabled through the POR input the user can not enable
it through the DEVDISR register in software. However, if a SerDes port is enabled through the POR input
the user can disable it through the DEVDISR register in software. Disabling a SerDes port through
software should be done on a temporary basis. Power is always required for the SerDes interface, even if
the port is disabled through either mechanism.
for a SerDes port. The termination recommendations must be followed for each port.
If the high-speed SerDes port requires complete or partial termination, the unused pins should be
terminated as described in this section.
The following pins must be left unconnected (floating):
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1
2
Notes:
Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the
SerDes port mode. If the port is in x8 PCI Express mode, no termination is required because all pins are being used.
If the port is in x1/x2/x4 PCI Express mode, termination is required on the unused pins. If the port is in x4 Serial
RapidIO mode termination is required on the unused pins.
If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes are
required. Termination of the SerDes port should follow what is required when the port is enabled through both POR
input and DEVDISR. See Note 1 for more information.
Disabled through DEVDISR
Enabled through DEVDISR
Local Bus - If parity is not used, tie LDP[0:3] to ground via a 4.7 kΩ resistor, tie LPBSE to OV
via a 4.7 kΩ resistor (pull-up resistor). For systems which boot from Local Bus (GPCM)-controlled
flash, a pullup on LGPL4 is required.
SerDes - Receiver lanes configured for PCI Express are allowed to be disconnected (as would
occur when a PCI Express slot is connected but not populated). Directions for terminating the
SerDes signals is discussed in
SDn_TX[7:0]
Guidelines for High-Speed Interface Termination
SerDes Interface
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Table 72. SerDes Port Enabled/Disabled Configurations
SerDes port is disabled (and cannot be
SerDes port is disabled (through POR
(Reference Clock not required)
(Reference Clock not required)
Complete termination required
Complete termination required
Disabled through POR input
Section 20.5.1, “Guidelines for High-Speed Interface
enabled through DEVDISR)
Table 72
input)
describes the possible enabled/disabled scenarios
Same termination requirements as when
the port is enabled through POR input
SerDes port is disabled after software
Partial termination may be required
Enabled through POR input
(Reference Clock is required)
(Reference Clock is required)
SerDes port is enabled
disables port
Freescale Semiconductor
Termination.”
1
2
DD