mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 105

• Manufacturer Part Number: mpc8641
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

18 Clocking
This section describes the PLL configuration of the MPC8641. Note that the platform clock is identical to
the MPX clock.
18.1
Table 64
specifications for the memory bus.
provides the clocking for the Local bus.
Freescale Semiconductor
37.This pin is only an output in FIFO mode when used as Rx Flow Control.
38.This pin functions as cfg_dram_type[0 or 1] at reset and MUST BE VALID BEFORE HRESET ASSERTION in device sleep
39. Should be pulled to ground if unused (such as in FIFO, MII and RMII modes).
40. See
41. The phase between the output clocks TSEC1_GTX_CLK and TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps.
42. For systems which boot from Local Bus (GPCM)-controlled flash, a pullup on LGPL4 is required.
Special Notes for Single Core Device:
S1 . Solder ball for this signal will not be populated in the single core package.
S2 . The PLL filter from V
S3 . This pin should be pulled to GND for the single core device.
S4 . No special requirement for this pin on single core device. Pin should be tied to power supply as directed for dual core.
e600 core processor frequency
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
for ratio settings.
mode.
The phase between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK (ports 3 and 4) is no more than 100 ps.
(2–10 kΩ) resistor. See
Section 18.4.2, “Platform to FIFO
Name
provides the clocking specifications for the processor cores and
Characteristic
Clock Ranges
1
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Table 63. MPC8641 Signal Reference by Functional Block (continued)
DD
Section 20.2.1, “PLL Power Supply
_Core1 to AV
Table 64. Processor Core Clocking Specifications
Section 18.2, “MPX to SYSCLK PLL Ratio,”
Package Pin Number
Min
800
DD
1000 MHz
Table 66
Restrictions” for clock speed limitations for this pin when used in FIFO mode.
_Core1 should be removed. AV
1000
Max
provides the clocking for the Platform/MPX bus and
Maximum Processor Core Frequency
Min
800
1250MHz
Filtering” for more details.
1250
Max
Min
800
DD
Pin Type
1333MHz
and
_Core1 should be pulled to ground with a weak
Section 18.3, “e600 to MPX clock PLL Ratio,”
1333
Max
Table 65
Power Supply
Min
800
1500 MHz
provides the clocking
1500
Max
MHz
Unit
Notes
Table 67
Clocking
Notes
1, 2
105