mpc8641 Freescale Semiconductor, Inc, mpc8641 Datasheet - Page 20

• Manufacturer Part Number: mpc8641
• Description: Integrated Host Processor Hardware Specifications
• Manufacturer: Freescale Semiconductor, Inc

RESET Initialization
5
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8641.
Table 12
20
Required assertion time of HRESET
Minimum assertion time for SRESET_0 & SRESET_1
Platform PLL input setup time with stable SYSCLK
before HRESET negation
Input setup time for POR configs (other than PLL
config) with respect to negation of HRESET
Input hold time for all POR configs (including PLL
config) with respect to negation of HRESET
Maximum valid-to-high impedance time for actively
driven POR configs with respect to negation of
HRESET
Notes:
1. SYSCLK is the primary clock input for the MPC8641.
2 This is related to HRESET assertion time. Stable PLL configuration inputs are required when a stable SYSCLK is
(Platform and E600) PLL lock times
Local bus PLL
Note:
1.The PLL lock time for e600 PLLs require an additional 255 MPX_CLK cycles.
applied. See the MPC8641D Integrated Host Processor Reference Manual for more details on the power-on reset
sequence.
RESET Initialization
provides the PLL lock times.
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Table 11
Parameter/Condition
Parameter/Condition
provides the RESET initialization AC timing specifications.
Table 11. RESET Initialization Timing Specifications
Table 12. PLL Lock Times
Min
Min
100
100
—
—
—
3
4
2
Max
Max
100
50
—
—
—
—
—
5
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Unit
Unit
μs
μs
μs
μs
Freescale Semiconductor
Notes
Notes
—
—
1
2
1
1
1
1