mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 95

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68331
USER’S MANUAL
*Use this value when function is not required for chip-select operation.
0 = ASYNC*
1 = SYNC
The MODE bit determines whether chip-select assertion simulates an asynchronous
bus cycle, or is synchronized to the M6800-type bus clock signal (ECLK) available on
ADDR23 (refer to 4.3 System Clock for more information on ECLK).
The BYTE field controls bus allocation for chip-select transfers. Port size, set when a
chip select is enabled by a pin assignment register, affects signal assertion. When an
8-bit port is assigned, any BYTE field value other than %00 enables the chip select
signal. When a 16-bit port is assigned, however, BYTE field value determines when
the chip select is enabled. The BYTE fields for CS[10:0] are cleared during reset. How-
ever, both bits in the boot ROM option register (CSORBT) BYTE field are set (%11)
when the reset signal is released.
The R/W field causes a chip-select signal to be asserted only for a read, only for a
write, or for both read and write. Use this field in conjunction with the STRB bit to gen-
erate asynchronous control signals for external devices.
The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Se-
lecting address strobe causes a chip-select signal to be asserted synchronized with
the address strobe. Selecting data strobe causes a chip-select signal to be asserted
synchronized with the data strobe. This bit has no effect in synchronous mode.
The DSACK field specifies the source of data strobe acknowledge signals used in
asynchronous mode. It also allows the user to optimize bus speed in a particular ap-
plication by controlling the number of wait states that are inserted.
The SPACE field determines the address space in which a chip select is asserted. An
access must have the space type represented by SPACE encoding in order for a chip-
select signal to be asserted.
The IPL field contains an interrupt priority mask that is used when chip-select logic is
set to trigger on external interrupt acknowledge cycles. When the SPACE field is set
MODE
00 = Disable
01 = Lower
10 = Upper
*11 = Both
BYTE
Table 4-22 Option Register Function Summary
Freescale Semiconductor, Inc.
For More Information On This Product,
01 = Read
00 = Rsvd
10 = Write
11 = Both
R/W
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
0 = AS
1 = DS
STRB
1010 = 10 WAIT
1011 = 11 WAIT
1100 = 12 WAIT
1101 = 13 WAIT
1111 = External
0000 = 0 WAIT 00 = CPU SP
0001 = 1 WAIT 01 = User SP 001 = Priority 1
0010 = 2 WAIT 10 = Supv SP 010 = Priority 2
0011 = 3 WAIT 11 = S/U SP* 011 = Priority 3
0100 = 4 WAIT
0101 = 5 WAIT
0110 = 6 WAIT
0111 = 7 WAIT
1000 = 8 WAIT
1001 = 9 WAIT
1110 = F term
DSACK
SPACE
100 = Priority 4
101 = Priority 5
110 = Priority 6
111 = Priority 7
000 = All*
IPL
0 = Off*
1 = On
AVEC
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