mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 185

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68331
USER’S MANUAL
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
4B, 5B External Clock Rise and Fall Time
Num
Num
39A
46A
47A
47B
12A
2, 3
4, 5
1A
1B
9A
9C
39
46
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
F1
11
12
13
1
6
7
8
9
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time
Mode Select Hold Time
RESET Assertion Time
RESET Rise Time
Frequency of Operation (32.768 kHz crystal)
Clock Period
ECLK Period
External Clock Input Period
Clock Pulse Width
Clock Rise and Fall Time
Clock High to Address, FC, SIZE, RMC Valid
Clock High to Address, Data, FC, SIZE, RMC High Impedance
Clock High to Address, FC, SIZE, RMC Invalid
Clock Low to AS, DS, CS Asserted
AS to DS or CS Asserted (Read)
Clock Low to IFETCH, IPIPE Asserted
Address, FC, SIZE, RMC Valid
Clock Low to AS, DS, CS Negated
Clock Low to IFETCH, IPIPE Negated
AS, DS, CS Negated to
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
to AS, CS Asserted
Address, FC, SIZE Invalid (Address Hold)
Table A-6 16.78 MHz AC Timing, (Continued)
13
(V
(V
DD
DD
Freescale Semiconductor, Inc.
12
Characteristic
Characteristic
and V
and V
For More Information On This Product,
Table A-6a 20.97 MHz AC Timing
3
ELECTRICAL CHARACTERISTICS
DDSYN
DDSYN
5
4
Go to: www.freescale.com
3
= 5.0 Vdc
= 5.0 Vdc
2
11
10%, V
5%, V
SS
SS
= 0 Vdc, T
= 0 Vdc, T
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLDD
SCLDS
SCLDH
t
t
t
t
t
t
t
t
t
CHAZx
CHAZn
t
RWAS
t
HRPW
t
t
t
t
DOCH
CHDH
RADC
BNHN
t
t
t
t
CHAV
t
DABA
BKST
BKHT
RSTA
RSTR
XCHL
t
CLSA
STSA
AVSA
CLSN
RWA
AIHT
t
ECW
CLIN
SNAI
t
t
AIST
MSS
MSH
t
Ecyc
Xcyc
CLIA
t
XCrf
CW
GH
GA
cyc
Crf
t
A
f
rf
A
= T
= T
L
L
to T
to T
0.13
47.7
47.7
18.8
23.8
Min
150
512
Min
381
183
–10
H
90
15
40
15
10
15
10
20
10
10
H
—
—
—
—
—
—
2
1
5
0
0
0
0
4
0
0
0
0
2
2
2
)
)
20.97
Max
Max
30
28
29
10
23
47
23
10
22
23
22
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
8
5
MHz
Unit
Unit
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
A-9
A