mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 91

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mc68331cpv20b1

Manufacturer Part Number
mc68331cpv20b1
Description
Mc68331 32 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68331
USER’S MANUAL
Chip-select assertion can be synchronized with bus control signals to provide output
enable, read/write strobe, or interrupt acknowledge signals. Chip select logic can also
generate DSACK and AVEC signals internally. Each signal can also be synchronized
with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, ad-
dress, type of access, transfer size, and interrupt priority (in the case of interrupt ac-
knowledge) to parameters stored in chip-select registers. If all parameters match, the
appropriate chip-select signal is asserted. Select signals are active low. If a chip-select
function is given the same address as a microcontroller module or an internal memory
array, an access to that address goes to the module or array, and the chip-select sig-
nal is not asserted. The external address and data buses do not reflect the internal ac-
cess.
All chip-select circuits are configured for operation out of reset. However, all chip-se-
lect signals except CSBOOT are disabled, and cannot be asserted until the BYTE field
in the corresponding option register is programmed to a nonzero value, selecting a
1. Can be decoded to provide additional address space.
2. Varies depending upon peripheral memory size.
Freescale Semiconductor, Inc.
ADDR[23:0]
DATA[15:0]
MCU
CSBOOT
CLKOUT
For More Information On This Product,
DSACK
Figure 4-17 Basic MCU System
CS3
R/W
CS5
IRQ
FC
SIZ
AS
DS
SYSTEM INTEGRATION MODULE
1
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SIZ
CLK
AS
DSACK
DS
CS
IACK
IRQ
ADDR[15:0]
DATA[15:0]
ADDR[23:0]
DATA[15:8]
CS
R/W
ADDR[23:0]
DATA[7:0]
CS
R/W
PERIPHERAL
ASYNC BUS
MEMORY
MEMORY
2
2
2
32 EXAMPLE SYS BLOCK
4-49
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