mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 63

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.4.3 Operand Alignment
4.4.4 Misaligned Operands
MC68331
USER’S MANUAL
tain the other 16 bits. The operation for an 8-bit port is similar, but requires four read
cycles. The addressed device uses the DSACK signals to indicate the port width. For
instance, a 16-bit device always returns DSACK for a 16-bit port (regardless of wheth-
er the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle
begins.
Operand bytes are designated as shown in Figure 4-8. OP[0:3] represent the order of
access. For instance, OP0 is the most significant byte of a long-word operand, and is
accessed first, while OP3, the least significant byte, is accessed last. The two bytes of
a word-length operand are OP0 (most significant) and OP1. The single byte of a byte-
length operand is OP0.
The EBI data multiplexer establishes the necessary connections for different combi-
nations of address and data sizes. The multiplexer takes the two bytes of the 16-bit
bus and routes them to their required positions. Positioning of bytes is determined by
the size and address outputs. SIZ1 and SIZ0 indicate the remaining number of bytes
to be transferred during the current bus cycle. The number of bytes transferred is equal
to or less than the size indicated by SIZ1 and SIZ0, depending on port width.
ADDR0 also affects the operation of the data multiplexer. During an operand transfer,
ADDR[23:1] indicate the word base address of the portion of the operand to be ac-
cessed, and ADDR0 indicates the byte offset from the base.
CPU32 architecture uses a basic operand size of 16 bits. An operand is misaligned
when it overlaps a word boundary. This is determined by the value of ADDR0. When
ADDR0 = 0 (an even address), the address is on a word and byte boundary. When
ADDR0 = 1 (an odd address), the address is on a byte boundary only. A byte operand
is aligned at any address; a word or long-word operand is misaligned at an odd ad-
dress.
Long Word
Three Byte
Operand
Word
Byte
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 4-8 Operand Byte Order
SYSTEM INTEGRATION MODULE
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31
OP0
24 23
OP1
OP0
Byte Order
16 15
OP2
OP1
OP0
8 7
OP3
OP2
OP1
OP0
0
4-21
4