mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 79

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.6.2 Reset Control Logic
4.6.3 Reset Mode Selection
MC68331
USER’S MANUAL
Software Watchdog
SIM reset control logic determines the cause of a reset, synchronizes reset assertion
if necessary to the completion of the current bus cycle, and asserts the appropriate re-
set lines. Reset control logic can drive four different internal signals.
All resets are gated by CLKOUT. Resets are classified as synchronous or asynchro-
nous. An asynchronous reset can occur on any CLKOUT edge. Reset sources that
cause an asynchronous reset usually indicate a catastrophic failure; thus the reset
control logic responds by asserting reset to the system immediately. (A system reset,
however, caused by the CPU32 RESET instruction, is asynchronous but does not in-
dicate any type of catastrophic failure).
Synchronous resets are timed (CLKOUT) to occur at the end of bus cycles. The inter-
nal bus monitor is automatically enabled for synchronous resets. When a bus cycle
does not terminate normally, the bus monitor terminates it.
Refer to Table 4-15 for a summary of reset sources.
Internal single byte or aligned word writes are guaranteed valid for synchronous re-
sets. External writes are also guaranteed to complete, provided the external configu-
ration logic on the data bus is conditioned as shown in Figure 4-15.
The logic states of certain data bus pins during reset determine SIM operating config-
uration. In addition, the state of the MODCLK pin determines system clock source and
the state of the BKPT pin determines what happens during subsequent breakpoint as-
sertions. Table 4-16 is a summary of reset mode selection options.
Loss of Clock
Power Up
External
System
1. EXTRST (external reset) drives the external reset pin.
2. CLKRST (clock reset) resets the clock module.
3. MSTRST (master reset) goes to all other internal circuits.
4. SYSRST (system reset) indicates to internal circuits that the CPU has executed
HALT
Type
Test
a RESET instruction.
External
Source
Monitor
Monitor
CPU32
Clock
Test
EBI
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-15 Reset Source Summary
Timing
Asynch
Asynch
Asynch
Asynch
Synch
Synch
Synch
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
Internal HALT Assertion
(e.g. Double Bus Fault)
RESET Instruction
Loss of Reference
External Signal
Test Mode
Time Out
Cause
V
DD
Reset Lines Asserted by Controller
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
MSTRST
—
CLKRST
CLKRST
CLKRST
CLKRST
CLKRST
—
—
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
EXTRST
4-37
4