mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 223

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

FRZBM — Freeze Bus Monitor Enable
SLVEN — Factory Test Mode Enabled
SHEN[1:0] — Show Cycle Enable
SUPV — Supervisor/Unrestricted Data Space
MM — Module Mapping
IARB[3:0] — Interrupt Arbitration Field
D.3.2 SIMTR — System Integration Test Register
D.3.3 SYNCR — Clock Synthesizer Control Register
W — Frequency Control (VCO)
X — Frequency Control Bit (Prescale)
MC68331
USER’S MANUAL
15
W
0
This field determines what the EBI does with the external bus during internal transfer
operations.
The SUPV bit places the SIM global registers in either supervisor or user data space.
Determines SIM interrupt arbitration priority. The reset value is $F (highest priority), to
prevent SIM interrupts from being discarded during initialization.
SIMTR is used for factory test only.
RESET:
0 = When FREEZE is asserted, the bus monitor continues to operate.
1 = When FREEZE is asserted, the bus monitor is disabled.
0 = IMB is not available to an external master.
1 = An external bus master has direct access to the IMB.
0 = Registers with access controlled by the SUPV bit are accessible from either the
1 = Registers with access controlled by the SUPV bit are restricted to supervisor
0 = Internal modules are addressed from $7FF000 – $7FFFFF.
1 = Internal modules are addressed from $FFF000 – $FFFFFF.
SYNCR determines system clock operating frequency and mode of operation.
Clock frequency is determined by SYNCR bit settings as follows:
0 = Base VCO frequency
1 = VCO frequency multiplied by four
0 = VCO frequency divided by four (base system clock frequency)
1 = VCO frequency divided by two (system clock frequency doubles)
14
X
0
user or supervisor privilege level.
access only.
13
1
1
Freescale Semiconductor, Inc.
1
Y
For More Information On This Product,
1
1
Go to: www.freescale.com
REGISTER SUMMARY
8
1
EDIV
7
0
6
0
0
5
0
0
SLIMP
U
4
SLOCK
U
3
RSTEN
2
0
STSIM
1
0
$YFFA02
$YFFA04
STEXT
D-15
0
0
.
D