mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 50

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4
4.2.12 Low-Power STOP Operation
4-8
Use the following expression to calculate timer period.
Interrupt priority and vectoring are determined by the values of the periodic interrupt
request level (PIRQL) and periodic interrupt vector (PIV) fields in the periodic interrupt
control register (PICR).
Content of PIRQL is compared to the CPU32 interrupt priority mask to determine
whether the interrupt is recognized. Table 4-6 shows priority of PIRQL values. Be-
cause of SIM hardware prioritization, a PIT interrupt is serviced before an external in-
terrupt request of the same priority. The periodic timer continues to run when the
interrupt is disabled.
The PIV field contains the periodic interrupt vector. The vector is placed on the IMB
when an interrupt request is made. The vector number used to calculate the address
of the appropriate exception vector in the exception vector table. Reset value of the
PIV field is $0F, which corresponds to the uninitialized interrupt exception vector.
When the CPU32 executes the LPSTOP instruction, the current interrupt priority mask
is stored in the clock control logic, internal clocks are disabled according to the state
of the STSIM bit in the SIMCR, and the MCU enters low-power stop mode. The bus
monitor, halt monitor, and spurious interrupt monitor are all inactive during low-power
stop.
During low-power stop, the clock input to the software watchdog timer is disabled and
the timer stops. The software watchdog begins to run again on the first rising clock
edge after low-power stop ends. The watchdog is not reset by low-power stop. A ser-
vice sequence must be performed to reset the timer.
The periodic interrupt timer does not respond to the LPSTOP instruction, but continues
to run during LPSTOP. To stop the periodic interrupt timer, PITR must be loaded with
a zero value before the LPSTOP instruction is executed. A PIT interrupt, or an external
interrupt request, can bring the MCU out of the low-power stop condition if it has a
higher priority than the interrupt mask value stored in the clock control logic when low-
power stop is initiated. LPSTOP can be terminated by a reset.
PIT Period
Freescale Semiconductor, Inc.
Table 4-6 Periodic Interrupt Priority
For More Information On This Product,
PIRQL
000
001
010
011
100
101
110
111
SYSTEM INTEGRATION MODULE
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--------------------------------------------------------------------------------------------- -
PIT Modulus Prescaler Value 4
EXTAL Frequency
Periodic Interrupt Disabled
Interrupt Priority Level 1
Interrupt Priority Level 2
Interrupt Priority Level 3
Interrupt Priority Level 4
Interrupt Priority Level 5
Interrupt Priority Level 6
Interrupt Priority Level 7
Priority Level
USER’S MANUAL
MC68331