mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 84

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules
4.6.6 Reset Timing
4-42
As a rule, module pins that are assigned to general-purpose I/O ports go to active high-
impedance state following reset. Other pin states are determined by individual module
control register settings. Refer to sections concerning modules for details. However,
during power-up reset, module port pins may be in an indeterminate state for a short
period. Refer to 4.6.7 Power-On Reset for more information.
The RESET input must be asserted for a specified minimum period for reset to occur.
External RESET assertion can be delayed internally for a period equal to the longest
bus cycle time (or the bus monitor time-out period) in order to protect write cycles from
being aborted by reset. While RESET is asserted, SIM pins are either in an inactive,
high impedance state or are driven to their inactive states.
When an external device asserts RESET for the proper period, reset control logic
clocks the signal into an internal latch. The control logic drives the RESET pin low for
an additional 512 CLKOUT cycles after it detects that the RESET signal is no longer
being externally driven, to guarantee this length of reset to the entire system.
CS[9:6]/ADDR[22:19]/PC[6:3]
IRQ[7:1]/PF[7:1]
SIZ[1:0]/PE[7:6]
CS10/ADDR23
CS5/FC2/PC2
CS3/FC0/PC0
MODCLK/PF0
DSACK0/PE0
DSACK1/PE1
CSE/BGACK
ADDR[18:0]
DATA[15:0]
Mnemonic
AVEC/PE2
CSBOOT
CLKOUT
FC1/PC1
CSM/BG
CS0/BR
AS/PE5
DS/PE4
RESET
BERR
HALT
RMC
R/W
TSC
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 4-18 SIM Pin Reset States
SYSTEM INTEGRATION MODULE
High-Z Output
High-Z Output
Mode Select
Mode Select
Mode Select
State While
Asserted
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Asserted
Disabled
Disabled
Go to: www.freescale.com
RESET
Output
1
1
1
1
1
1
1
1
1
ADDR[18:0]
DATA[15:0]
MODCLK
Function
CSBOOT
CLKOUT
DSACK0
DSACK1
IRQ[7:1]
SIZ[1:0]
CS[9:6]
RESET
BERR
AVEC
CS10
HALT
CSM
RMC
CSE
CS0
CS5
CS3
R/W
TSC
FC1
Pin
DS
AS
Pin State After RESET Released
Pin State
Unknown
Unknown
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
1
1
1
1
1
0
1
1
1
ADDR[22:19]
ADDR[18:0]
DATA[15:0]
Function
CSBOOT
CLKOUT
ADDR23
BGACK
RESET
PF[7:1]
PE[7:6]
BERR
HALT
TSC
PE5
PE2
PE4
PE0
PE1
FC2
FC1
FC0
PF0
R/W
PE3
Pin
BG
BR
USER’S MANUAL
Pin State
Unknown
Unknown
Unknown
Unknown
Unknown
Unknown
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
MC68331
1
0