mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 48

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mc68331cpv20b1

Manufacturer Part Number
mc68331cpv20b1
Description
Mc68331 32 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
4
4-6
Both writes must occur before time-out in the order listed, but any number of instruc-
tions can be executed between the two writes.
Watchdog clock rate is affected by the software watchdog prescale (SWP) and soft-
ware watchdog timing (SWT) fields in SYPCR.
SWP determines system clock prescaling for the watchdog timer and determines that
one of two options, either no prescaling or prescaling by a factor of 512, can be select-
ed. The value of SWP is affected by the state of the MODCLK pin during reset, as
shown in Table 4-3. System software can change SWP value.
The SWT field selects the divide ratio used to establish software watchdog time-out
period. Time-out period is given by the following equations.
or
Table 4-4 shows the ratio for each combination of SWP and SWT bits. When SWT[1:0]
are modified, a watchdog service sequence must be performed before the new time-
out period can take effect.
Figure 4-3 is a block diagram of the watchdog timer and the clock control for the pe-
riodic interrupt timer.
Table 4-3 MODCLK Pin and SWP Bit During Reset
Time-out Period
Freescale Semiconductor, Inc.
Table 4-4 Software Watchdog Ratio
For More Information On This Product,
Time-out Period
0 (External Clock)
1 (Internal Clock)
SYSTEM INTEGRATION MODULE
MODCLK
SWP
0
0
0
0
1
1
1
1
Go to: www.freescale.com
=
------------------------------------------------------------------------------------ -
EXTAL Frequency Divide Ratio
SWT
00
01
10
11
00
01
10
11
=
------------------------------------------------ -
EXTAL Frequency
Divide Ratio
1 ( 512)
0 ( 1)
SWP
Ratio
2
2
2
2
2
2
2
2
11
13
15
18
20
22
24
1
9
USER’S MANUAL
MC68331

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