mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 69

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.5.4.1 Breakpoint Acknowledge Cycle
4.5.4.1.1 Software Breakpoints
4.5.4.1.2 Hardware Breakpoints
MC68331
USER’S MANUAL
Breakpoints stop program execution at a predefined point during system development.
Breakpoints can be used alone or in conjunction with the background debugging
mode. The following paragraphs discuss breakpoint processing when background de-
bugging mode is not enabled. See SECTION 5 CENTRAL PROCESSING UNIT for
more information on exception processing and the background debugging mode.
In M68300 microcontrollers, both hardware and software can initiate breakpoints.
The CPU32 BKPT instruction allows the user to insert breakpoints through software.
The CPU responds to this instruction by initiating a breakpoint-acknowledge read cy-
cle in CPU space. It places the breakpoint acknowledge (%0000) code on AD-
DR[19:16], the breakpoint number (bits [2:0] of the BKPT opcode) in ADDR[4:2], and
%0 (indicating a software breakpoint) on ADDR1.
The external breakpoint circuitry decodes the function code and address lines and re-
sponds by either asserting BERR or placing an instruction word on the data bus and
asserting DSACK.
If the bus cycle is terminated by DSACK, the CPU32 reads the instruction on the data
bus and inserts the instruction into the pipeline. (For 8-bit ports, this instruction fetch
may require two read cycles.)
If the bus cycle is terminated by BERR, the CPU32 then performs illegal-instruction
exception processing: it acquires the number of the illegal-instruction exception vector,
computes the vector address from this number, loads the content of the vector address
into the PC, and jumps to the exception handler routine at that address.
Assertion of the BKPT input initiates a hardware breakpoint. The CPU responds by ini-
tiating a breakpoint-acknowledge read cycle in CPU space. It places $00001E on the
STOP BROADCAST
ACKNOWLEDGE
ACKNOWLEDGE
BREAKPOINT
LOW POWER
INTERRUPT
Figure 4-11 CPU Space Address Encoding
Freescale Semiconductor, Inc.
FUNCTION
For More Information On This Product,
2
1 1 1
2
1 1 1
2
1 1 1
CODE
SYSTEM INTEGRATION MODULE
0
0
0
Go to: www.freescale.com
23
23
23
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CPU SPACE CYCLES
CPU SPACE
TYPE FIELD
19
19
19
16
16
16
ADDRESS BUS
4
BKPT#
LEVEL
CPU SPACE CYC TIM
2
1
T 0
0
0
0
1
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