mc68331cpv20b1 Freescale Semiconductor, Inc, mc68331cpv20b1 Datasheet - Page 180

• Manufacturer Part Number: mc68331cpv20b1
• Description: Mc68331 32 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

A
A-4
Notes for Tables A–4 and A–4a
1. All internal registers retain data at 0 Hz
2 This parameter is periodically sampled rather than 100% tested.
3. Assumes that a low-leakage external filter network is used to condition clock synthesizer input voltage. Total
4. Proper layout procedures must be followed to achieve specifications.
5. Assumes that stable V
6. Internal VCO frequency (f
7. Stability is the average deviation from the programmed frequency measured over the specified interval at
Num
external resistance from the XFC pin due to external leakage must be greater than 15 M to guarantee this
specification. Filter network geometry can vary depending upon operating environment (See 4.3 System
Clock).
the time V
required for PLL lock after changing the W and Y frequency control bits in the synthesizer control register
(SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP.
divide-by-two circuit that is not in the synthesizer feedback loop. When X = 0, the divider is enabled, and f
= f
maximum specified f
maximum f
ble external clock signal. Noise injected into the PLL circuitry via V
oscillator frequency increase the C
straint on control system operation, this parameter should be measured during functional testing of the final
system.
1
2
3
4
5
6
VCO
PLL Reference Frequency Range
System Frequency
On-Chip PLL System Frequency
External Clock Operation
PLL Lock Time
VCO Frequency
Limp Mode Clock Frequency
CLKOUT Stability
SYNCR X bit = 0
SYNCR X bit = 1
Short term (5 s interval)
Long term (500 s interval)
4. When X = 1, the divider is disabled, and f
DD
sys
. Measurements are made with the device powered by filtered supplies and clocked by a sta-
and V
Table A-4a 20.97 MHz Clock Control Timing
(V
Characteristic
Freescale Semiconductor, Inc.
DD
DDSYN
2,3,4,5
sys
6
For More Information On This Product,
and V
DDSYN
2,3,4,7
.
1
VCO
are valid until RESET is released. This specification also applies to the period
ELECTRICAL CHARACTERISTICS
DDSYN
is applied, and that the crystal oscillator is stable. Lock time is measured from
) is determined by SYNCR W and Y bit values. The SYNCR X bit controls a
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stab
= 5.0 Vdc 5%, V
32.768 kHz reference)
percentage for a given interval. When clock stability is a critical con-
Symbol
C
f
f
f
VCO
t
f
limp
sys
lpll
stab
SS
ref
sys
= 0 Vdc, T
= f
VCO
0.131
–0.05
–0.5
Min
A
25
dc
dc
—
—
—
—
2. X must equal one when operating at
= T
DDSYN
L
to T
and V
2 (f
f
H,
sys
f
sys
20.97
20.97
20.97
sys
Max
0.05
0.5
50
20
max/2
max
SS
max)
and variation in crystal
USER’S MANUAL
MHz
MHz
MHz
Unit
kHz
ms
MC68331
sys