mc68hc908sr12 Freescale Semiconductor, Inc, mc68hc908sr12 Datasheet - Page 306

• Manufacturer Part Number: mc68hc908sr12
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Multi-Master IIC Interface (MMIIC)
Data Sheet
306
MMSRW — MMIIC Slave Read/Write Select
MMRXAK — MMIIC Receive Acknowledge
MMCRCBF — CRC Data Buffer Full Flag
This bit indicates the data direction when the module is in slave mode.
It is updated after the calling address is received from a master
device. MMSRW = 1 when the calling master is reading data from the
module (slave transmit mode). MMSRW = 0 when the master is
writing data to the module (receive mode).
When this bit is cleared, it indicates an acknowledge signal has been
received after the completion of eight data bits transmission on the
bus. When MMRXAK is set, it indicates no acknowledge signal has
been detected at the 9th clock; the module will release the SDA line
for the master to generate STOP or repeated START condition. Reset
sets this bit.
This flag is set when the CRC data register (MMCRCDR) is loaded
with a CRC byte for the current received or transmitted data.
In transmit mode, after a byte of data has been sent (MMTXIF = 1),
the MMCRCBF will be set when the CRC byte has been generated
and ready in the MMCRCDR. The content of the MMCRCDR should
be copied to the MMDTR for transmission.
In receive mode, the MMCRCBF is set when the CRC byte has been
generated and ready in MMCRCDR, for the current byte of received
data.
The MMCRCBF bit is cleared when the CRC data register is read.
Reset also clears this bit.
1 = Received address matches MMADR
0 = Received address does not match
1 = Slave mode transmit
0 = Slave mode receive
1 = No acknowledge signal received at 9th clock
0 = Acknowledge signal received at 9th clock
1 = Data ready in CRC data register (MMCRCDR)
0 = Data not ready in CRC data register (MMCRCDR)
Multi-Master IIC Interface (MMIIC)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor