mc68hc908sr12 Freescale Semiconductor, Inc, mc68hc908sr12 Datasheet - Page 238

• Manufacturer Part Number: mc68hc908sr12
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Analog-to-Digital Converter (ADC)
15.4.6 Result Justification
Data Sheet
238
The conversion result may be formatted in four different ways.
All four of these modes are controlled using MODE0 and MODE1 bits
located in the ADC clock control register (ADICLK).
Left justification will place the eight most significant bits (MSB) in the
corresponding ADC data register high (ADRH). This may be useful if the
result is to be treated as an 8-bit result where the least significant two
bits, located in the ADC data register low (ADRL) can be ignored.
However, you must read ADRL after ADRH or else the interlocking will
prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC
data register high (ADRH) and the eight LSB bits in ADC data register
low (ADRL). This mode of operation typically is used when a 10-bit
unsigned result is desired.
Left justified sign data mode is similar to left justified mode with one
exception. The MSB of the 10-bit result, AD9 located in ADRH is
complemented. This mode of operation is useful when a result,
represented as a signed magnitude from mid-scale, is needed.
Finally, 8-bit truncation mode will place the eight MSBs in ADC data
register low (ADRL). The two LSBs are dropped. This mode of operation
is used when compatibility with 8-bit ADC designs are required. No
interlocking between ADRH and ADRL is present.
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Left justified
Right justified
Left justified sign data mode
8-bit truncation
Analog-to-Digital Converter (ADC)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor