ml670100 Oki Semiconductor, ml670100 Datasheet - Page 63

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

4.4.2.1
4.4.2.2
The interrupt controller uses the following procedure to decide interrupt priority.
(1)
(2)
(3)
Interrupt Priority Order
Interrupt Sequence
(1)
(2)
(3)
If the interrupt level specified for the corresponding source is higher than the highest
level flagged in the Current Interrupt Level Register (CILR), which holds interrupt level
flags for the interrupts currently being processed, the interrupt controller asserts the IRQ
signal to send the CPU an IRQ exception request.
If there are multiple interrupt requests satisfying the above condition, the interrupt
controller selects the one with the highest interrupt level.
If there are multiple interrupt requests with the highest interrupt level, the interrupt
controller selects the one with the highest fixed priority. The interrupt controller then
writes the interrupt level assigned to the selected interrupt request to the Interrupt
Request Level Register (IRLR) and the interrupt number to the Interrupt Number
Register(INR).
Interrupt arrives.
The interrupt controller detects an external interrupt request from the nEIR[7:0] pins or
an internal interrupt request from the on-chip peripherals.
Interrupt is noted.
The interrupt controller sets the corresponding pending flag in the Interrupt Request
Registers 0 to 3 (IRRn, n=0 - 3) to indicate that an interrupt request has been received.
Interrupt passes to CPU.
If an interrupt level of 0 is not masking interrupt requests from that source, the interrupt
controller runs through the following three steps.
• It asserts the exception signal to the CPU.
• It determines the interrupt level.
• It determines the interrupt number.
If there are any interrupt requests with interrupt levels higher than the highest level
flagged in the Current Interrupt Level Register (CILR), which holds interrupt level
flags for the interrupts currently being processed, the interrupt controller asserts the
nIRQ signal to send the CPU an IRQ exception request.
The interrupt controller selects the highest interrupt level from among the outstanding
interrupt requests and stores that level in the Interrupt Request Level Register (IRLR).
The interrupt controller selects the interrupt source with the highest priority using the
procedure in Section 4.4.2.1 "Interrupt Priority Order" above and places its number in
the Interrupt Number Register (INR).
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