ml670100 Oki Semiconductor, ml670100 Datasheet - Page 190
ml670100
Manufacturer Part Number
ml670100
Description
Ml670100 Is A High-performance 32-bit Microcontroller
Manufacturer
Oki Semiconductor
Datasheet
1.ML670100.pdf
(204 pages)
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11-34
SYSCLK
(CLKOUT)
nRAS0
nRAS1
nCAS
(1) Simultaneous bank access and CBR refresh requests
(2) DRAM access immediately after powering on or a system reset
A CBR refresh request arising during access to a DRAM bank (2 or 3) is postponed until
that access is complete. Similarly, an access request arising during CBR refresh is
postponed until that CBR refresh cycle is complete.
When the power is first applied and after the power supply voltage has reached the
specified level, some DRAM devices supporting CBR refresh require a pause followed by
specified minimum number of CBR refresh cycles. If such is the case, set up the Refresh
Control Register (RFCON) and the Refresh Cycle Control Register (RCCON) to provide
these cycles.
Fixed at one cycle
CBR refresh for DRAM bank 2
Figure 11.29 : CBR Refresh Timing
Fixed at three cycles
Fixed at one cycle
CBR refresh for DRAM bank 3
Fixed at three cycles
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