ml670100 Oki Semiconductor, ml670100 Datasheet - Page 46

• Manufacturer Part Number: ml670100
• Description: Ml670100 Is A High-performance 32-bit Microcontroller
• Manufacturer: Oki Semiconductor

3.3
3.3.1
3.3.2
3-6
Asserting the external reset signal (nRST) asserts the LSI's internal reset signal for the
It is up to the signal source to assert the signal long enough to cover both the crystal oscillator
circuit stabilization period and the PLL lock time.
Watchdog Timer (WDT) counter overflow signal (WDTOV) asserts the internal reset signal for
nine clock cycles, resetting the CPU and all on-chip peripherals except the I/O ports, and the
Clock Control Register (CKCON) in the CPU control unit. By not initializing the I/O ports and
CKCON, the LSI maintains the I/O port direction settings (input/output), I/O port pin function
settings (primary/secondary), I/O port output levels and CKCON setting (clock frequency
divider ratio) in effect before the reset.
System Resets
This LSI has two sources for system resets:
External Reset Signal (nRST)
assert time plus nine clock cycles, resetting the CPU and on-chip peripherals and initializing
the following registers.
Watchdog Timer (WDT) Counter Overflow
•
•
The LSI resets the HLT bit in the Standby Control Register (SBYCON) to "0" to wake
from HALT mode.
The LSI initializes the Reset Status Register (RSTST) to 0x00000001.
• External reset signal (nRST)
• Watchdog Timer (WDT) counter overflow signal (WDTOV)
• The LSI initializes the Standby Control Register (SBYCON) to 0x00000000 and
• The LSI initializes the Reset Status Register (RSTST) to 0x00000000.
wakes from HALT mode.