ml670100 Oki Semiconductor, ml670100 Datasheet
ml670100
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ml670100 Summary of contents
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... ML670100 Users’ Manual Semiconductor Version 1.0 of April, 1999 ...
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application ...
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Overview 1.1 Features 1.2 Block Diagram 1.3 Pins 1.3.1 Pin Layout 1.3.2 Pin Functions 1.3.3 Treatment of Unused Pins 1.3.4 Configurations of Pins and I/O ports 2 CPU 2.1 CPU Operating States 2.2 Switching State 2.3 Memory Formats 2.4 ...
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Undefined instruction 2.9.8 Exception vectors 2.9.9 Exception priorities 2.10 Reset 3 CPU Control Functions 3.1 Overview 3.1.1 Pins 3.1.2 Control Registers 3.2 Control Registers 3.2.1 Standby Control Register (SBYCON) 3.2.2 Clock Control Register (CKCON) 3.2.3 Reset Status Register (RSTST) ...
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External IRQ Control Register (EIRCON) 4.3.6 Interrupt Request Registers (IRRn, n 4.3.7 Interrupt Level Control Registers (ILCONn, n=0 - 15) 4.4 Interrupt Processing 4.4.1 External Fast Interrupt Requests 4.4.2 External and ...
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WDT Interval Timer Operation 7 Flexible Timer 7.1 Overview 7.1.1 Block Diagram 7.1.2 Pins 7.1.3 Control Registers 7.2 Control Registers 7.2.1 Timer Control Registers (TMnCON, n 7.2.2 Timer Status Registers (TMnST, ...
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Control Registers 8.2.1 ASI Control Register (ASICON) 8.2.2 ASI Buffer Register (ASBUF) 8.2.3 ASI Shift Registers 8.2.4 ASI Status Register (ASIST) 8.2.5 ASI Test Control Register (ASTSCON) 8.2.6 Baud Rate Timer Counter (ASBTMC) 8.2.7 Baud Rate Timer Register (ASBTMR) ...
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Control Registers 10.2 Control Registers 10.2.1 AD Control Register H (ADHCON) 10.2.2 AD Control Register L (ADLCON) 10.2.3 AD Status Register (ADST) 10.2.4 AD Result Registers (ADCRn, n 10.3 Analog-to-Digital Converter (ADC) Operation 11 ...
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External Access Functions Common to All Banks 11.3.5 Accessing Bank 0 Internal Memory Areas 11.4 Bus Arbitration 11.4.1 Bus Access and Priority 11.4.2 Requesting and Obtaining Bus Access 11.4.3 Lock Operation 11.5 Standby Operation 11.6 Connecting External Memory 11.6.1 ...
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viii ...
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Overview 1.1 Features 1.2 Block Diagram 1.3 Pins 1.3.1 Pin Layout 1.3.2 Pin Functions 1.3.3 Treatment of Unused Pins 1.3.4 Configurations of Pins and I/O ports 1-2 1-4 1-5 1-5 1-6 1-10 1-11 1-1 ...
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... Features ML670100 is a high-performance 32-bit microcontroller combining a RISC-based, 32-bit CPU core - the ARM7TDMI developed by ARM Limited - with memory (ROM and RAM) and such peripheral circuits as timers, serial ports, and an analog-to-digital converter. This combination of 32-bit data processing, built-in memory, and on-chip peripherals make it ideal for controlling equipment requiring both high speed and high functionality ...
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Serial ports - One asynchronous serial port (UART) with built-in baud rate generator - Two clock synchronous serial ports • Analog-to-digital converter - 8-bit resolution - Analog input port with eight channels • Interrupt controller - Support for 28 ...
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Block Diagram Figure 1-1 gives a block diagram for this LSI. TDI* TDO* nTRST* TMS* TCK* DBGEN* DBGRQ* DBGACK* nRST nEA DBSEL TEST VDD GND AVDD AGND TMIN/TMOUT[5:0]* TMCLK[1:0]* ASI_TXD* ASI_RXD* CSI1_TXD* CSI1_RXD* CSI1_SCLK* CSI0_TXD* CSI0_RXD* CSI0_SCLK* Asterisks indicate ...
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Pins 1.3.1 Pin Layout Figure 1-2 gives the pin layout for this LSI. PIO3[5]/nEIR[5] 109 PIO3[6]/nEIR[6] 110 PIO3[7]/nEIR[7] 111 GND 112 PIO4[0]/TMIN[0]/TMOUT[0] 113 PIO4[1]/TMIN[1]/TMOUT[1] 114 PIO4[2]/TMIN[2]/TMOUT[2] 115 PIO4[3]/TMIN[3]/TMOUT[3] 116 PIO4[4]/TMIN[4]/TMOUT[4] 117 PIO4[5]/TMIN[5]/TMOUT[5] 118 PIO4[6]/TMCLK[0] 119 PIO4[7]/TMCLK[1] 120 GND 121 ...
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Pin Functions Table 1.1 lists the functions of each pin. Table 1.1 : Pin Functions Type Signal Name Pin Address XA23-XA16 bus XA15-XA0 Data bus XD15-XD8 XD7-XD0 Bus nCS0 control nCS1 signals nRD nWRL nWRH nWRE nLB nHB nRAS0 ...
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Table 1.1 : Pin Functions Type Signal Name Pin Number Bus nCAS 95 control signals nWH 97 nWL 94 nXWAIT 101 nBREQ 27 nBACK 28 Interrupts nEFIQ 67 nEIR[7:0] 111-104 Timers TMIN[5:0] 118-113 TMOUT[5:0] 118-113 TMCLK[1:0] 120,119 Serial ASI_TXD 130 ...
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Table 1.1 : Pin Functions Type Signal Name Pin Serial CSI0_SCLK ports CSI1_TXD CSI1_RXD CSI1_SCLK Analog-to- VREF digital converter AI[7:0] Debugging TDI interface TDO nTRST TMS TCK DBGEN DBGRQ DBGACK 1-8 I/O Direction Description Number 123 Bi-directional This pin accepts/provides ...
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Table 1.1 : Pin Functions Type Signal Name Pin Number I/O ports PIO8[7:0] 36-29 PIO7[7:0] 28-24 21-19 PIO6[7:0] 18-11 PIO5[7:0] 130-123 PIO4[7:0] 120-113 PIO3[7:0] 111-104 PIO2[7:0] 101-94 PIO1[7:0] 88-81 PIO0[7:0] 66-59 Clock OSC0 133 control OSC1 134 CLKOUT 131 FSEL ...
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Table 1.1 : Pin Functions Type Signal Name Pin System TEST control Power VDD supply GND AVDD AGND 1.3.3 Treatment of Unused Pins Table 1.2 lists the connections for unused pins. Table 1.2 : Treatment of Unused Pins Pin Name(s) ...
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Configurations of Pins and I/O ports (1) Input Pins (nRST, nEA, DBSEL, TEST, nEFIQ, FSEL, PLLEN, VCOM) Input pins (high impedance) (2) Output Pin (CLKOUT) (3) Tri-state output pins (XA23 - XA1, nLB/XA0, nCS0, nRD, nWRE/nWRL) Output enable signal ...
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I/O port A (I/O ports without secondary functions) PIO6[7:0], PIO7[5:0] PMm [n] POm [n] (6) I/O port B (I/O ports with secondary functions of input) PIO2[7], PIO3[7:0] , PIO4[7:6] , PIO5[6] , PIO5[4], PIO5[1] , PIO7[6] , PIO8[7] , ...
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I/O port C (I/O ports with secondary functions of output) PIO5[7], PIO5[5], PIO5[2], PIO7[7], PIO8[6], PIO8[0] PMm [n] POm [n] Secondary function output signal PFSm [n] Read PIm [n] PIOm [n] 1-13 ...
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I/O port D (I/O ports with secondary functions of tri-state output) PIO0[7:0], PIO2[6:0] PMm [n] Secondary function output enable signal POm [n] Secondary function output signal PFSm [n] 1-14 Read PIm [n] PIOm [n] ...
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I/O port E (I/O ports with secondary functions of input and output) PIO1[7:0], PIO4[5:0], PIO5[3], PIO5[0] PMm [n] Secondary function output enable signal POm [n] Secondary function output signal Secondary function input signal PFSm [n] Read PIm [n] PIOm ...
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1-16 ...
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CPU This LSI uses as its CPU the ARM7TDMI core developed by ARM Limited. This CPU offers the programmer a choice of two states: ARM state, executing 32-bit ARM instructions, and THUMB state, executing 16-bit THUMB instructions, a subset ...
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CPU Operating States From the programmer's point of view, the CPU can be in one of two states: ARM state which executes 32-bit, word-aligned ARM instructions. THUMB state which operates with 16-bit, halfword-aligned THUMB instructions. In this state, the ...
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Instruction Length Instructions are either 32 bits long (in ARM state bit long (in THUMB state). 2.5 Data Types The CPU supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to four-byte ...
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The ARM state register set In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non-User) modes, mode-specific banked registers are switched in. Figure 2.2 : Register organization in ...
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ARM State General Registers and Program Counter System & User FIQ R8_fiq R9 R9_fiq R10 R10_fiq R11 R11_fiq R12 R12_fiq R13 R13_fiq R14 ...
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The THUMB state register set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register ...
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The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way: • THUMB state R0-R7 and ARM state R0-R7 are identical • THUMB state CPSR and SPSRs and ...
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The Program Status Registers The CPU contains a Current Program Status Register (CPSR), plus four Saved Program Status Registers (SPSRs) for use by exception handlers. These registers • hold information about the most recently performed ALU operation • control ...
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The mode bits Reserved bits Table 2.1 : PSR mode bit values M[4:0] 10000 10001 10010 10011 11011 11111 2.9 Exceptions Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an ...
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Action on entering an exception When handling an exception, the CPU: 1 Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered from ARM state, then the address of the next ...
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Table 2.2 : Exception entry/exit Return Instruction BL MOV PC, R14 SWI MOVS PC, R14_svc UDEF MOVS PC, R14_und FIQ SUBS PC, R14_fiq, #4 IRQ SUBS PC, R14_irq, #4 RESET Note : 1 Where PC is the address of the ...
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Software interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb): MOV PC, R14_svc ...
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Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1 Reset 2 FIQ 3 IRQ Lowest priority: 4 Undefined Instruction, software interrupt. Not all ...
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2-14 ...
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CPU Control Functions 3.1 Overview 3.1.1 Pins 3.1.2 Control Registers 3.2 Control Registers 3.2.1 Standby Control Register (SBYCON) 3.2.2 Clock Control Register (CKCON) 3.2.3 Reset Status Register (RSTST) 3.3 System Resets 3.3.1 External Reset Signal (nRST) 3.3.2 Watchdog Timer ...
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Overview CPU control functions for this LSI include the following. • Reset control This function controls the system reset function for initializing the CPU and on-chip peripherals. • Clock control This function controls the oscillator circuit based on a ...
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Control Registers Table 3.2 lists the control registers for the CPU control unit. Reads from these control registers takes exactly one clock cycle; writes, at least two. Modifying the standby control (SBYCON) or clock control (CKCON) register requires two ...
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The LSI ignores the above transition requests when (1) a preceding interrupt request has set a bit in the Interrupt Request Registers (IRRn, n "1" and the corresponding interrupt level for the interrupt in ...
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Reset Status Register (RSTST) The Reset Status Register (RSTST 32-bit read-only register indicating the trigger for the most recent system reset. The external reset signal (nRST) sets this register to 0x00000000; the Watchdog Timer (WDT) counter overflow ...
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System Resets This LSI has two sources for system resets: • External reset signal (nRST) • Watchdog Timer (WDT) counter overflow signal (WDTOV) 3.3.1 External Reset Signal (nRST) Asserting the external reset signal (nRST) asserts the LSI's internal reset ...
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Clock Signals The basic clock signal is either the oscillation clock from the oscillator circuit or an external clock signal. Table 3.3 : Clock Sources Clock source External source Crystal oscillator If the PLLEN input enables PLL operation, specify ...
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Standby Mode Writing "1" to the HLT bit in the Standby Control Register (SBYCON) switches this LSI to HALT mode. This mode suspends operation of the CPU but the peripheral circuits remain operational. The LSI remains in HALT mode ...
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Interrupt Controller 4.1 Overview 4.1.1 Block Diagram 4.1.2 Pins 4.1.3 Control Registers 4.2 Interrupt Sources 4.2.1 External Fast Interrupt Requests 4.2.2 External Interrupt Requests 4.2.3 Internal Interrupt Requests 4.2.4 Interrupt Source Mappings 4.3 Control Registers 4.3.1 Interrupt Number Register ...
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Overview The interrupt controller manages interrupt requests from 9 external sources and 19 internal ones and passes them on to the CPU as interrupt request (IRQ) or fast interrupt request (FIQ) exception requests. It supports eight interrupt levels for ...
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Figure 4.1 : Block Diagram for Interrupt Controller (INT) 4-3 ...
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Pins Table 4.1 lists the pins connected to the interrupt controller. Table 4.1 : Interrupt Controller (INT) Pins Pin Name External fast interrupt request External interrupt request 4.1.3 Control Registers Table 4.2 lists the control registers for the interrupt ...
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Interrupt Sources There are three types of interrupt requests: external fast interrupt requests producing FIQ exception requests, external interrupt requests producing IRQ exception requests, and internal interrupt requests producing IRQ exception requests. An external fast interrupt request sends the ...
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Internal Interrupt Requests Internal interrupt requests come from the following on-chip peripherals: - Analog-to-Digital Converter (ADC) - Clock Synchronous Serial Interfaces (CSI0 and CSI1) - Asynchronous Serial Interface (ASI) - Time Base Generator (TBG) - Flexible Timer (FTM) If ...
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Table 4.3 : Interrupt Source Mappings Interrupt Interrupt Request Source Number Pending Flag nEFIQ - EFIQR nEIR[7] 31 IRR3[7] nEIR[6] 30 IRR3[6] nEIR[5] 29 IRR3[5] nEIR[4] 28 IRR3[4] nEIR[3] 27 IRR3[3] nEIR[2] 26 IRR3[2] nEIR[1] 25 IRR3[1] nEIR[0] 24 IRR3[0] ...
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Control Registers 4.3.1 Interrupt Number Register (INR) The Interrupt Number Register (INR 8-bit read-only register that holds the interrupt number assigned to the unmasked interrupt request with the highest priority. After a system reset, it contains an ...
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CILR[7]: CILR[6]: :: CILR[1]: 4.3.3 Interrupt Request Level Register (IRLR) The Interrupt Request Level Register (IRLR 8-bit read-only register that holds the interrupt level (obtained from an interrupt level field (ILRn, n=0 - 31) in the Interrupt Level ...
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External FIQ Control Register (EFIQCON) The External FIQ Control Register (EFIQCON 8-bit read/write register that notes external fast interrupt requests, tracks the signal level at the external fast interrupt request (nEFIQ) pin, and controls masking of external ...
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External IRQ Control Register (EIRCON) The External IRQ Control Register (EIRCON 8-bit read/write register specifying the detection methods ("L" level sensing or falling edge sensing) for external interrupt requests from the nEIR[7:0] pins. After a system reset, ...
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Interrupt Request Registers (IRRn, n The Interrupt Request Registers (IRRn, n are 8-bit read/write registers containing numbered flags tracking external and internal interrupt requests. After a system reset, they ...
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ILCON0 0 ILR1 ILCON1 0 ILR3 ILCON2 0 ILR5 ILCON3 ILCON4 0 ILR9 ILCON5 0 ILR11 ILCON6 0 ILR13 ILCON7 0 ILR15 ILCON8 0 ILR17 ILCON9 0 ILR19 ILCON10 0 ILR21 ILCON11 0 0 ...
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Interrupt Processing 4.4.1 External Fast Interrupt Requests If there is an external fast interrupt request and the external FIQ mask (EFIQM) flag in the External FIQ Control Register (EFIQCON) does not mask it, the interrupt controller sends the CPU ...
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Interrupt Priority Order The interrupt controller uses the following procedure to decide interrupt priority. (1) If the interrupt level specified for the corresponding source is higher than the highest level flagged in the Current Interrupt Level Register (CILR), which ...
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CPU accepts IRQ exception. If the CPU is accepting IRQ exception requests - that is, if the I bit in its Current Program Status Register (CPSR) is not masking them - it switches to IRQ exception handling, setting the ...
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IRQ handler processes level 2 interrupt. To enable interrupt requests with higher interrupt levels, the IRQ handler saves the Link Register (R14_irq) and the Saved Program Status Register (SPSR_irq) to the stack and then resets the I bit in ...
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Note : Before executing steps t17 and t18, the IRQ handler must set the I bit in CPSR to "1" to disable IRQ exceptions. t17. IRQ handler clears CILR[2]. Just before terminating level 2 interrupt processing, the IRQ handler clears ...
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Figure 4.9 : Example of Interrupt Level Control 4-19 ...
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Sampling Timing for External Interrupt Requests The interrupt controller samples the external fast interrupt request signal from the nEFIQ pin and the external interrupt request signals from the nEIR[7:0] pins and sets the corresponding interrupt request bits to "1" ...
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SYSCLK(CLKOUT) nEIR[n] (n=0-7) pin A bit in IRR3 (a) Using falling edge sensing for interrupt request detection SYSCLK(CLKOUT) nEIR[n] (n=0-7) pin A bit in IRR3 (b) Using "L" level sensing for interrupt request detection Figure 4.11 : Sampling Timing for ...
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Table 4.4 : Interrupt Response Times Step Delay between application of signal to pin and raising of interrupt request flag Wait for current instruction to complete execution Time required to save the PC and CPSR registers and load the vector ...
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I/O Ports 5.1 Overview 5.1.1 Control Registers 5.2 Control Registers 5.2.1 Port Output Registers (POn, n 5.2.2 Port Input Registers (PIn, n 5.2.3 Port Mode Registers ...
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Overview The I/O ports consist of nine 8-bit ports: PIOn (n=0 - 8). I/O directions are specified at the bit level. When configured for input, the pins use high-impedance input. In addition to their primary functions as I/O ports, ...
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Table 5.1 : Secondary Functions for I/O Port Pins Port Pin(s) Signal Name(s) PIO5[7] ASI_TXD PIO5[6] ASI_RXD PIO5[5] CSI1_TXD PIO5[4] CSI1_RXD PIO5[3] CSI1_SCLK PIO5[2] CSI0_TXD PIO5[1] CSI0_RXD PIO5[0] CSI0_SCLK PIO6[7:0] None PIO7[7] nBACK PIO7[6] nBREQ PIO7[5:0] None PIO8[7] TDI PIO8[6] ...
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Control Registers Table 5.2 lists the control registers for the I/O ports. Table 5.2 : I/O Port Control Registers Address Name 0x060_0600 Port Output Register 0 0x060_0601 Port Output Register 1 0x060_0602 Port Output Register 2 0x060_0603 Port Output ...
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Control Registers 5.2.1 Port Output Registers (POn, n Port Output Register n (POn, n 8-bit read/write register that holds the output data for I/O port PIOn. If the corresponding PIOn ...
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Port Mode Registers (PMn, n Port Mode Register n (PMn, n 8-bit read/write register that specifies the I/O directions for I/O port PIOn pins. These settings apply only to the ...
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Bit Descriptions The bits in PFS0 control the secondary pin functions for I/O port PIO0. Setting a bit to "1" configures the corresponding pin as part of the external address bus XA; resetting it to "0," I/O pin. ...
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Port Function Selection Register 7 (PFS7) Port Function Selection Register 7 (PFS7) activates PIO7 pin secondary functions at the bit level. After a system reset triggered by the external reset signal (nRST) , this register contains 0x00 ...
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I/O Port Operation 5.3.1 Configuration after System Reset A system reset triggered by the external reset signal (nRST) initializes PIOn pin functions to the following configurations: • PIO2[7] and PIO3 to PIO7 have their primary pin functions (I/O) and ...
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5-10 ...
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Time Base Generator 6.1 Overview 6.1.1 Block Diagram 6.1.2 Control Registers 6.2 Control Registers 6.2.1 Watchdog Timer Control Register (WDTCON) 6.2.2 Time Base Generator Control Register (TBGCON) 6.3 Time Base Generator (TBG) Operation 6.3.1 Time Base Counter (TBC) 6.3.2 ...
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Overview The main components of the Time Base Generator (TBG) are the Time Base Counter (TBC), a frequency divider which derives the time base clock signals for the on-chip peripherals from the system clock (SYSCLK) signal, and the Watchdog ...
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SYSCLK 8-bit Time Base Counter (TBC) Figure 6.1 : Block Diagram for Time Base Generator (TBG) 6.1.2 Control Registers Table 6.1 lists the control registers for the Time Base Generator (TBG). Table 6.1 : Time Base Generator (TBG) Control Registers ...
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Control Registers 6.2.1 Watchdog Timer Control Register (WDTCON) The Watchdog Timer Control Register (WDTCON 8-bit write-only register for starting the Watchdog Timer (WDT) and clearing its watchdog timer configuration, writing 0x3C to this ...
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Bit Descriptions Note Writing to any of the ITEN, ITM, and WDCK bits automatically resets the WDT internal counter to 0. ITEN This bit is only used when a "1" in the ITM bit configures the Watchdog Timer (WDT) as ...
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Time Base Generator (TBG) Operation 6.3.1 Time Base Counter (TBC) The Time Base Counter (TBC frequency divider which derives the time base clock signals for the on-chip peripherals from the system clock (SYSCLK) signal. Figure 6.4 shows ...
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Watchdog Timer (WDT) The Watchdog Timer (WDT 12-bit counter that counts pulses from an input clock in the range 32TBCCLK to 256TBCCLK. Although it is possible to indirectly clear the contents writing to the ...
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Time to Overflow the system clock (SYSCLK) frequency in MHz, t WDT, the time in microseconds that the Watchdog Timer (WDT) internal counter takes to overflow, is given by the following formula. t WDT = m ...
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Program flow Counter Contents Program writes Program writes 0x3C 0xC3 to start counter. to clear counter. 0xFFF 0x000 Less than tWDT (a)Program operating normally Program flow Counter Program writes Program writes Contents 0x3C 0xC3 to start counter. to clear counter. ...
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Writing only 0x3C (c) Not writing 0x3C and 0xC3 Figure 6.7 : Patterns for Runaway Programs 6-10 Program writes 0x3C to WDTCON to clear counter. Program writes 0xC3 to WDTCON to clear counter. Program writes 0x3C to WDTCON to ...
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WDT Interval Timer Operation Figure 6.8 illustrates WDT interval timer operation. Counter overflow produces a Watchdog Timer (WDT) interrupt request signal (WDINT). Counter Contents 0xFFF 0x000 WDTINT Program flow Overflow Overflow Program starts counter. Figure 6.8 : WDT Interval ...
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6-12 ...
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Flexible Timer 7.1 Overview 7.1.1 Block Diagram 7.1.2 Pins 7.1.3 Control Registers 7.2 Control Registers 7.2.1 Timer Control Registers (TMnCON, n 7.2.2 Timer Status Registers (TMnST, n 7.2.3 Timer ...
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Overview The Flexible Timer (FTM) consists of six 16-bit timer channels. Each channel offers independent choices of four operating modes and of eight count clocks. • Timer operating modes - Auto-reload timer (ART) - Compare out (CMO) - Pulse ...
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FTMOVn (n=0 - 5):Timer overflow interrupt request from Flexible Timer (FTM) channel n EVENTn (n=0 - 5):Capture event or compare match interrupt request from Flexible Timer (FTM) cannel n Figure 7.1 : Block Diagram for Flexible Timer (FTM) 7-3 ...
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Pins Table 7.1 lists the pins connected to the Flexible Timer (FTM). Table 7.1 : Flexible Timer (FTM) Pins Pin Name Symbol Timer Input/Output TMIN[5:0]/ TMOUT[5:0] Timer clock input TMCLK[1:0] 7.1.3 Control Registers Table 7.2 lists the control registers ...
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Table 7.2 : Flexible Timer (FTM) Control Registers Address Name 0x060_0130 Timer Control Register 3 0x060_0131 Timer Status Register 3 0x060_0132 Timer Counter 3 0x060_0134 Timer Register 3 0x060_0136 Timer General-Purpose Register 3 0x060_0138 Timer I/O Level Register 3 0x060_0139 ...
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Control Registers 7.2.1 Timer Control Registers (TMnCON, n Timer Control Register n (TMnCON, n 8-bit read/write register that specifies the operating mode and count clock for Flexible Timer (FTM) channel ...
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Bit Descriptions MOD This field specifies the operating mode for timer channel n. There are four choices: auto-reload timer (ART), compare out (CMO), pulse width modulation (PWM), and capture (CAP). TMCLK This field specifies the count clock for Timer Counter ...
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Bit Descriptions CM/CAPEV This flag indicates events as defined by the operating mode: - The auto-reload timer (ART) and pulse width modulation (PWM) modes do not modify this flag. - Compare out (CMO) mode sets it to "1" and generates ...
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Timer Registers (TMnR, n Timer Register n (TMnR, n 16-bit read/write register that holds the value that timer channel n loads into Timer Counter n (TMnC, n when ...
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Timer I/O Level Registers (TMnIOLV, n Timer I/O Level Register n (TMnIOLV, n 8-bit read/write register that, in the compare out (CMO) and pulse width modulation (PWM) modes, specifies the ...
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Bit Descriptions IOLV - Auto-reload timer (ART) mode does not use this field. - Compare out (CMO) mode uses this field to specify the output level for Timer Output n pin (TMOUT[n], n=0-5) through Timer Output Register n (TMnOUT, n=0-5)when ...
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Timer Output Registers (TMnOUT, n Timer Output Register n (TMnOUT, n 8-bit read/write register that holds the output level for Timer Output n pin (TMOUT[n], n=0 - 5). After a ...
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Timer Enable Register (TMEN) The Timer Enable Register (TMEN 8-bit read/write register for starting timer channels. After a system reset, this register contains 0x00. Bit TMnEN (n controls timer channel "0" ...
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Flexible Timer (FTM) Operation Each Flexible Timer (FTM) channel offers a choice of four operating modes: - Auto-reload timer (ART) - Compare out (CMO) - Pulse width modulation (PWM) - Capture (CAP) The MOD field in Timer Control Register ...
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Auto-Reload Timer (ART) Mode Setting the MOD field in Timer Control Register n (TMnCON, n 2’b00 (ART) configures timer channel n in auto-reload timer (ART) mode. When Timer Counter n (TMnC, n overflows, the ...
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TMnC contents 0xFFFF TMnGR value Starting value (from TMnR) 0x0000 FTMOVn EVENTn TMOUT [n]output for IOLV= 2'b00 and initial setting of "1" TMOUT [n]output for IOLV= 2'b01 and initial setting of "0" TMOUT [n]output for IOLV= 2'b10 and initial setting ...
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TMnC contents 0xFFFF TMnGR value Starting value (from TMnR) 0x0000 FTMOVn TMOUT[n] output for IOLV=2'b00 TMOUT[n] output for IOLV=2'b01 Figure 7.13 : Pulse Width Modulation (PWM) Operation 7.3.5 Capture (CAP) Mode Setting the MOD field in Timer Control Register n ...
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TMnC contents 0xFFFF Value 1 Value 2 Starting value (from TMnR) 0x0000 TMIN[n] input for IOLV=2’b01 TMnGR value FTMOVn EVENTn 7.3.6 Synchronizing Starts and Stops Simultaneously writing "1" to multiple TMnEN (n bits in the Timer Enable Register ...
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Signal Timing 7.4.1 Timer Clock Input Sampling Flexible Timer (FTM) channels 0 and 1 support external clock signals. Figure 7.15 shows the timing with which the timer channel samples the external clock signal from Timer Clock Input n pin ...
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Capture Trigger Input Sampling In capture (CAP) mode, a Flexible Timer (FTM) channel configures its Timer Input/Output n pin (TMIN[n]/TMOUT[n], n capture trigger input pin TMIN[n] (n=0 -5) with high-impedance input. Figure 7.16 shows the ...
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SYSCLK (CLKOUT) TMIN[n] Signal for loading TMnGR from TMnC TMnC TMnGR SYSCLK (CLKOUT) TMIN[n] Signal for loading TMnGR from TMnC TMnC TMnGR (b)IOLV specifies falling edges Figure 7.16 : Timing for Sampling Capture Trigger Signal and Loading TMnGR from TMnC ...
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Timer Output Timing In compare out (CMO) or pulse width modulation (PWM) mode, a Flexible Timer (FTM) channel configures its Timer Input/Output n pin (TMIN[n]/TMOUT[n], n timer output pin TMOUT[n] (n=0 - 5). Figure 7.17 ...
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Asynchronous Serial Interface 8.1 Overview 8.1.1 Block Diagram 8.1.2 Pins 8.1.3 Control Registers 8.2 Control Registers 8.2.1 ASI Control Register (ASICON) 8.2.2 ASI Buffer Register (ASBUF) 8.2.3 ASI Shift Registers 8.2.4 ASI Status Register (ASIST) 8.2.5 ASI Test Control ...
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Overview The Asynchronous Serial Interface (ASI serial port that frames (synchronizes) each character of information with start and stop elements. Parameters control transfer speed (using a dedicated baud rate generator), character length, number of stop bits, and ...
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ASI_TXD Receive shift ASI_RXD register ASBUF ASICON ASIST Figure 8.1 Block Diagram for Asynchronous Serial Interface (ASI) Figure 8.2 gives the structure of the baud rate generator (ASBGEN), which includes the following components: - Baud Rate Timer Counter (ASBTMC) - ...
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Figure 8.2 : Block Diagram for Baud Rate Generator (ASBGEN) 8.1.2 Pins Table 8.1 lists the pins connected to the Asynchronous Serial Interface (ASI). Table 8.1 : Asynchronous Serial Interface (ASI) Pins Pin Name Transmit data ...
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Control Registers 8.2.1 ASI Control Register (ASICON) The ASI Control Register (ASICON 8-bit read/write register that controls transmission and reception. After a system reset, this register contains 0x00, which specifies the default parameters of 8-bit character, 2 ...
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ASEVN This bit specifies the parity logic (odd or even) for the parity bit, if present, for transmit and receive operation. Setting it to "1" specifies even parity; writing "0," odd parity. ASPEN This bit enables/disables the parity bit for ...
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ASI Status Register (ASIST) The ASI Status Register (ASIST 8-bit read/write register containing transmit/ receive ready flags and error flags for errors detected during receive operations. The interface updates the lowest three bits upon completion of each ...
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Bit Descriptions ATRIRQ This flag indicates the transmit ready state. The interface sets this flag to "1" when it is ready to accept more transmit data - that is, when it transfers the contents of the transmit buffer (ASBUF) to ...
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ASI Test Control Register (ASTSCON) The ASI Test Control Register (ASTSCON 8-bit read/write register that simplifies the testing of asynchronous serial interface internals by looping the ASI channel's transmit output signal back to the receive input signal. ...
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Baud Rate Timer Counter (ASBTMC) The Baud Rate Timer Counter (ASBTMC 8-bit read/write register that contains the internal count for the baud rate generator (ASBGEN). Counter overflow produces the baud rate clock signal and a baud rate ...
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Baud Rate Control Register (ASBCON) The Baud Rate Control Register (ASBCON 8-bit read/write register that selects the Baud Rate Timer Counter (ASBTMC) count clock, starts and stops counting, indicates overflow, and selects the operating mode. After a ...
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BGMOD This bit selects the baud rate generator (ASBGEN) mode. Setting it to "1" configures ASBGEN as the baud rate generator for the Asynchronous Serial Interface (ASI). Resetting it to "0" selects auto-reload timer (ART) mode. Note that the latter ...
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Asynchronous Serial Interface (ASI) Operation 8.3.1 Baud Rate Generator (ASBGEN) Operation The baud rate generator (ASBGEN 8-bit timer that generates the baud rate clock for the Asynchronous Serial Interface (ASI). If not needed for that purpose, it ...
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Table 8.3 : Baud Rate and the Setting Value 4MHz f SYSCLK Baud n D rate 300 4 204 600 4 230 1200 4 243 2400 3 243 4800 2 243 9600 1 243 19200 - - 31250 1 252 ...
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Table 8.3 : Baud Rate and the Setting Value 14.7456MHz f SYSCLK Baud n D Error rate (%) 300 600 4 160 0 1200 4 208 0 2400 4 232 0 4800 4 244 0 9600 4 ...
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Setting Communications Parameters The program specifies the character length, number of stop bits, and the parity for transmission and reception with the ASI Control Register (ASICON). To enable reception, it must also set the ASRVEN bit in ASICON to ...
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Receiving Data To enable reception, the program must set the ASRVEN bit in the ASI Control Register (ASICON) to "1." Then, when the interface detects a start bit, it begins receiving one frame of data in the frame format ...
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8-18 ...
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Clock Synchronous Serial Interface 9.1 Overview 9.1.1 Block Diagram 9.1.2 Pins 9.1.3 Control Registers 9.2 Control Registers 9.2.1 CSI Control Registers 0,1 (CSInCON, n=0,1) 9.2.2 CSI Shift Registers 0,1 (CSInSFT, n=0,1) 9.2.3 CSI Status Registers 0,1 (CSInST, n=0,1) 9.2.4 ...
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Overview The Clock Synchronous Serial Interfaces 0,1 (CSIn, n=0,1) are two serial ports that transmit 8-bit data synchronized with internal or external clock signals. 9.1.1 Block Diagram Figure 9.1 gives a block diagram for Clock Synchronous Serial Interfaces 0,1 ...
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Pins Table 9.1 lists the pins connected to Clock Synchronous Serial Interfaces 0,1 (CSIn, n=0,1). Table 9.1 : Clock Synchronous Serial Interface (CSIn, n=0,1) Pins Pin Name Channel 0 transmit data Channel 0 receive data Channel 0 synchronization clock ...
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Control Registers 9.2.1 CSI Control Registers 0,1 (CSInCON, n=0,1) CSI Control Register n (CSInCON, n=0, 8-bit read/write register that controls transmission and reception by Clock Synchronous Serial Interface n (CSIn, n=0,1). After a system reset, this register ...
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CSI Shift Registers 0,1 (CSInSFT, n=0,1) CSI Shift Register n (CSInSFT, n=0, 8-bit read/write register that holds and shifts transmitted and received data for Clock Synchronous Serial Interface n (CSIn, n=0,1). After a system reset, this register ...
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CSI Status Registers 0,1 (CSInST, n=0,1) CSI Status Register n (CSInST, n=0, 8-bit read/write register giving the status of Clock Synchronous Serial Interface n (CSIn, n=0,1). Only the BUSY bit is writeable. After a system reset, this ...
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CSI Test Control Register (CSTSCON) The CSI Test Control Register (CSTSCON 8-bit read/write register that simplifies the testing of serial port internals by looping each CSI channel's transmit output signal back to its receive input signal. After ...
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Clock Synchronous Serial Interface (CSI) Operation CSI Shift Register n (CSInSFT, n=0, 8-bit shift register that simultaneously shifts bits in from the CSIn_RXD (n=0,1) pin and shifts bits out from the CSIn_TXD (n=0,1) pin using the synchronization ...
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In slave mode, the serial port ignores any clock pulses beyond the eighth. Writing "0" to the BUSY bit while a transfer is underway aborts the transfer and initializes Clock Synchronous Serial Interface n (CSIn, n=0,1) by clearing the SFTCT ...
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I/O Signal Timing 9.4.1 Master Mode I/O Signal Timing Figure 9.7 gives the I/O signal timing for master mode. The serial port feeds the synchronization clock signal to the CSIn_SCLK (n=0,1) pin, shifts the transmit data to the CSIn_TXD ...
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Slave Mode I/O Signal Timing Figure 9.8 gives the I/O signal timing for slave mode. The serial port samples the synchronization clock signal from the CSIn_SCLK (n=0,1) pin, shifts the transmit data to the CSIn_TXD (n=0,1) pin, and samples ...
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9-12 ...
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Analog-to-Digital Converter 10.1 Overview 10.1.1 Block Diagram 10.1.2 Pins 10.1.3 Control Registers 10.2 Control Registers 10.2.1 AD Control Register H (ADHCON) 10.2.2 AD Control Register L (ADLCON) 10.2.3 AD Status Register (ADST) 10.2.4 AD Result Registers ...
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Overview The Analog-to-Digital Converter (ADC 8-bit successive approximation analog-to-digital converter with eight analog input channels and four result registers. It offers two operating modes: scan mode, which sequentially converts the inputs from the selected set of four ...
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VREF AVDD AGND AI[0] Analog input channel selector AI[7] Control unit ADHCON ADLCON Figure 10.1 : Block Diagram for Analog-to-Digital Converter (ADC) ADCR0 ADCR1 Analog-to-digital converter ADCR2 ADCR3 ADINT ADST Peripheral bus ADINT: A/D conversion complete interrupt request 10-3 ...
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Pins Table 10.1 lists the pins connected to the Analog-to-Digital Converter (ADC). Table 10.1 : Analog-to-Digital Converter (ADC) Pins Pin Name Reference voltage Analog input channels 10.1.3 Control Registers Table 10.2 lists the control registers for the Analog-to-Digital Converter ...
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Control Registers 10.2.1 AD Control Register H (ADHCON) AD Control Register H (ADHCON 8-bit read/write register that specifies the operating mode and controls starting and stopping for the analog-to-digital converter. After a system reset, this register contains ...
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Bit Descriptions ADRUN This bit controls starting. Setting it to "1" starts A/D conversion. If the CONT bit is "0," the analog-to-digital converter automatically resets this bit to "0" and shuts down after four conversions for the scan modes and ...
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AD Control Register L (ADLCON) AD Control Register L (ADLCON 8-bit read/write register that specifies the conversion time (in clock cycles) per channel for the analog-to-digital converter. After a system reset, this register contains 0x00 ...
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The next Table gives the additional clock cycles required for the first conversion after writing "1" to the ADRUN bit in AD Control Register H (ADHCON). If the ADTM setting is 2'b01, for example, a scan of four input channels ...
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AD Result Registers (ADCRn, n The AD Result Registers (ADCRn, n are 8-bit read-only registers that hold the conversion results. After a system reset, these registers contain indeterminate values. ...
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Analog-to-Digital Converter (ADC) Operation The analog-to-digital converter's three operating modes fall into two types: the scan modes and select mode. AD Control Register H (ADHCON) specifies the mode. The scan modes sequentially convert analog inputs from four channels (CH0 ...
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Start A/D conversions with CH0 CH0 -CH3 scan mode Start CH4 A/D conversions with CH4 -CH7 scan mode Start End CH5 A/D conversion of channel 5 input with select mode Interrupt request (ADRUN reset to "0."ADERQ set to "1.") (1)Continuous ...
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ADCR0 A/D conversion result from channel 0 ADCR1 A/D conversion result from channel 1 ADCR2 A/D conversion result from channel 2 ADCR3 A/D conversion result from channel 3 (1) CH0 to CH3 scan mode ADCR0 A/D conversion result from channel ...
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External Memory Controller 11. 1 Overview 11.1.1 Block Diagram 11.1.2 Pins 11.1.3 Control Registers 11.1.4 Address Spaces 11.2 Control Registers 11.2.1 Bus Width Control Register (BWCON) 11.2.2 Wait Input Control Register (WICON) 11.2.3 Off Time Control Register (OTCON) 11.2.4 ...
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Overview The External Memory Controller (XMC) generates control signals for accessing external memory (ROM, SRAM, DRAM, etc.), and other devices with addresses in the external memory space. It also controls the core bus, and peripheral bus during data transfers. ...
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Block Diagram Figure 11.1 gives a block diagram for the External Memory Controller (XMC), which includes the following components: - Bus Width Control Register (BWCON), which controls the external data bus width for each bank - Wait Input Control ...
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Core data bus Core address bus Figure 11.1 : Block Diagram for External Memory Controller (XMC) 11-4 PWCON BACON SRAM bank(0 and 1) control unit BWCON WICON OTCON DR2CON DRAM bank DR3CON (2 and 3) AT2CON control unit AT3CON DW2CON ...
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Pins Table 11.1 lists the pins connected to the External Memory Controller (XMC). Table 11.1 : External Memory Controller (XMC) Pins Pin Name External address bus External data bus Bank 0 chip select Bank 1 chip select SRAM bank ...
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Table 11.1 : External Memory Controller (XMC) Pins Pin Name Bus request Bus acknowledgment Data bus width selection Internal ROM selection 11.1.3 Control Registers Table 11.2 lists the control registers for the External Memory Controller (XMC). Table 11.2 : External ...
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Address Spaces The core architecture supports an address space of 4 gigabytes, but this LSI uses only the first 64 megabytes, divided into four equal banks. Table 11.3 outlines the address assignments for these banks. Table 11.3 : Address ...
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Note: Do not access addresses between 0x00000000 and 0x006FFFFF for which there is no internal ROM, internal RAM, or control register physically present or addresses 0x00700000 to 0x007FFFFF. Doing so produces unreliable operation. Bank 1 is for external devices (ROM, ...
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Control Registers 11.2.1 Bus Width Control Register (BWCON) The Bus Width Control Register (BWCON 8-bit read/write register that controls the external data bus width for each bank. After a system reset, this register contains a value that ...
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Wait Input Control Register (WICON) The Wait Input Control Register (WICON 8-bit read/write register that controls sampling of nXWAIT input to insert wait cycles during access to external devices for each bank. After a system reset, this ...
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Off Time Control Register (OTCON) The Off Time Control Register (OTCON 8-bit read/write register that specifies the number of system clock (SYSCLK) cycles ("off time") inserted when changing banks or changing from read access to write access ...
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Programmable Wait Control Register (PWCON) The Programmable Wait Control Register (PWCON 8-bit read/write register whose two halves specify the number of programmable wait cycles automatically inserted for accesses to the SRAM banks (0 and 1). After a ...
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Bus Access Control Register (BACON) The Bus Access Control Register (BACON 8-bit read/write register that specifies the access methods for 16-bit bus access to the SRAM banks (0 and 1). One access method uses two Byte Select ...
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DRAM Bank 2 and 3 Control Registers (DRnCON, n=2,3) The DRAM Bank n Control Register (DRnCON, n=2, 8-bit read/write register that controls access to DRAM bank n, specifying the row address shift for the multiplexed address, the ...
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BE The Burst Enable (BE) bit specifies the access mode (random access or high-speed paged) for bank n. Setting it to "1" specifies high-speed paged mode; resetting it to "0," random access mode. 11.2.7 DRAM Bank 2 and 3 Access ...
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DRAM Bank 2 and 3 Programmable Wait Control Registers (DWnCON, n=2,3) The DRAM Bank n Programmable Wait Control Register (DWnCON, n=2, 8-bit read/write register that specifies the number of wait cycles automatically added to the CAS assertion ...
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Refresh Timer Counter (RFTCN) The Refresh Timer Counter (RFTCN 8-bit read/write decrementing counter that controls the timing for CAS-before-RAS (CBR) refresh cycle requests for the DRAM banks (2 and 3). It uses a time base clock from ...
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Refresh Timing Control Register (RTCON) The Refresh Timing Control Register (RTCON 8-bit read/write register that specifies the RAS precharge time (t 3) back from self-refresh mode to normal operation mode. After a system reset, this register contains ...
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Refresh Control Register (RFCON) The Refresh Control Register (RFCON 8-bit read/write register that controls CAS- before- RAS (CBR) refresh and self-refresh operation for the DRAM banks (2 and 3) and specifies the count clock for the Refresh ...
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Bit Descriptions CLKS The Clock Selection (CLKS) field specifies the count clock for the Refresh Timer Counter (RFTCN). The choices are the time base clocks 2TBCCLK to 256TBCCLK. RSR The Self-Refresh (RSR) bit switches to and from DRAM self-refresh operation. ...
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Cycle Trace Control Register (CTCON) The Cycle Trace Control Register (CTCON), used only during application development is an 8-bit read/write register that adjusts CPU operation to emulate the in-circuit emulator's bus trace mode. Setting the CT bit to "1" ...
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Address Space Access This LSI supports an address space of 64 megabytes. The core actually supports an address space of 4 gigabytes, but other circuits ignore the top six bits (A31 to A26). The next two bits (XA25 and ...
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Addresses 0x00700000 to 0x007FFFFF are a reserved area and must not be used. - Addresses 0x00800000 to 0x008FFFFF are for external devices (ROM, RAM, or I/O devices). Note : Do not access addresses between 0x00000000 and 0x006FFFFF for which ...
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Accessing External Memory in SRAM Banks (0 and 1) The external memory areas in the SRAM banks (0 and 1) are designed primarily for direct connection to SRAM devices. Accessing them automatically generates the appropriate strobe signals (nCS0, nCS1, ...
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Read cycle SYSCLK (CLKOUT) nCS0 XA23 - XA0 nRD XD15 - XD0 nWRH/nWRL Figure 11.18 : SRAM Bank Access Timing with Two Programmable Wait Cycles Read cycle Program 2 wait + nXWAIT SYSCLK (CLKOUT) nCS0 XA23 - XA0 nRD XD15 ...
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Half Word Access Two access methods are available for 16-bit bus access to the SRAM banks (0 and 1): with one Write Enable signal and two Byte Select signals (nWRE , nHB and nLB) or with two Write Enable ...
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Accessing External Memory in DRAM Banks (2 and 3) The external memory areas in the DRAM banks (2 and 3) are designed primarily for direct connection to DRAM devices. Accessing them automatically generates an address signal multiplexing the upper ...
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Basic Access Basic access, access without wait cycles DRAM bank ( takes two clock cycles for a read or a write. Figure 11.21 shows the basic access timing for external memory areas in these two ...
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RAS-to-CAS Delay The RAS-to-CAS Delay (RCD) bit in the DRAM Bank 2 and 3 Access Timing Control Registers (ATnCON, n=2,3) adjusts the t nRAS and nCAS signals, for bank clock cycles to match the ...
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CAS Access Wait Cycles The CAS Access Wait Added (CAWA) field in the DRAM Bank 2 and 3 Programmable Wait Control Registers (DWnCON, n=2,3) adjusts the number of wait cycles automatically added to the CAS assertion time during access ...
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Input Wait Cycles Bits 2 and 3 in the Wait Input Control Register (WICON) enable/disable the use of nXWAIT input to insert additional wait cycles for each bank. Setting a bit to "1" enables sampling for the corresponding ...
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SYSCLK (CLKOUT) XA15 - XA1 nRAS nCASH nCASL nWE nWH nWL nCAS XD15 - XD0 Figure 11.26 : Half Word Write Access Timing for DRAM Banks (2 and 3) 11.3.3.5 High-Speed Paged Mode (Burst) Access The Burst Enable (BE) bit ...
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Refresh Access The External Memory Controller (XMC) offers two types of DRAM refresh functions: a CAS- before-RAS (CBR) refresh function and two self-refresh functions. 11.3.3.6.1 CAS-before-RAS (CBR) Refresh Function Setting either CBRR bit in the Refresh Control Register (RFCON) ...
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SYSCLK (CLKOUT) nRAS0 nRAS1 Fixed at one cycle nCAS CBR refresh for DRAM bank 2 (1) Simultaneous bank access and CBR refresh requests A CBR refresh request arising during access to a DRAM bank ( postponed until ...
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Self-Refresh Functions These functions are for use with self-refreshing DRAM devices, which switch to self-refresh mode when the controller accesses them with CAS-before-RAS access and then asserts the nRAS and nCAS signals for longer than the specified interval. (See ...
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External Access Functions Common to All Banks 11.3.4.1 Off Time Control This LSI divides addresses in its external memory areas into four banks. Because of the different data output hold times for the devices in these banks, the following ...
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SYSCLK (CLKOUT) nCS0 nCS1 XA23 - XA0 nRD XD15 - XD0 Figure 11.32 : Access Timing with Off Time (b) 11.3.4.2 Store Buffer The External Memory Controller (XMC) uses a single-stage store buffer to permit access to internal devices (internal ...
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Accessing Bank 0 Internal Memory Areas The bank 0 internal memory areas consist of four 2-megabyte areas assigned to internal ROM, internal RAM, control registers on the core bus, and control registers on the peripheral bus. Access to the ...
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Bus Arbitration 11.4.1 Bus Access and Priority The External Memory Controller (XMC) arbitrates access to the external bus by two types of bus masters: the CPU and external devices. External devices cannot access the core and peripheral buses inside ...
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Table 11.5 : Pins in High-Impedance States when Bus Release Always XA15 - 1 nLB/XA0 XD7 - 0 nCS0 nRD nWRE/nWRL Granting an external device access to the external bus has the following effects on external memory access and DRAM ...
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Standby Operation When the LSI switches to HALT mode, the External Memory Controller (XMC) switches to HALT mode at the end of the current bus cycle. Even in HALT mode, the controller still grants external bus access to external ...
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Connecting External Memory 11.6.1 Connecting ROM Figure 11.36 shows sample configurations for external ROMs connected to memory bank 0. Both ground the nEA pin to specify execution from the external ROM. If the ROM has a data width of ...
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XA0 XA1 XA2 XA17 XA18 XD0 XD1 XD6 XD7 nCS0 nRD DBSEL GND nEA (1) ROM with 8-bit data width Figure 11.36 : Connecting External ROM 512K X 8 ROM A17 A18 nCE ...
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Connecting SRAM Figure 11.37 shows sample configurations with the external data bus width to memory bank 1 set to 16 bits for connecting SRAMs with data widths bits. Connecting the nEA pin to V its ...