adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 6

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
0xFFFF FFFF
0xFFE0 0000
0xFFC0 0000
0xFFB0 1000
0xFFB0 0000
0xFFA1 4000
0xFFA1 0000
0xFFA0 0000
0xFF90 8000
0xFF90 4000
0xFF90 0000
0xFF80 8000
0xFF80 4000
0xFF80 0000
0xEF00 0000
0x2040 0000
0x2030 0000
0x2020 0000
0x2010 0000
0x2000 0000
0x0800 0000
0x0000 0000
Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map
Figure 4. Internal Connection of Flash Memory (ADSP-BF539Fx)
ADSP-BF539F
PACKAGE
ADDR19-1
DATA15-0
V DDEXT
AMS3-0
RESET
ARDY
CORE MMR REGISTERS (2M BYTE)
SYSTEM MMR REGISTERS (2M BYTE)
RESERVED
SCRATCHPAD SRAM (4K BYTE)
RESERVED
INSTRUCTION SRAM / CACHE (16K BYTE)
INSTRUCTION SRAM (64K BYTE)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTE)
DATA BANK B SRAM (16K BYTE)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTE)
DATA BANK A SRAM (16K BYTE)
RESERVED
RESERVED
ASYNC MEMORY BANK 3 (1M BYTE) OR
ASYNC MEMORY BANK 2 (1M BYTE) OR
ASYNC MEMORY BANK 1 (1M BYTE) OR
ASYNC MEMORY BANK 0 (1M BYTE) OR
RESERVED
SDRAM MEMORY (16M BYTE TO 512M BYTE)
AWE
GND
ON-CHIP FLASH (ADSP-BF539F ONLY)
ON-CHIP FLASH (ADSP-BF539F ONLY)
ON-CHIP FLASH (ADSP-BF539F ONLY)
ON-CHIP FLASH (ADSP-BF539F ONLY)
ARE
A18-0
WE
RY/BY
DQ15-0
VSS
VCC
BYTE
CE
RESET
OE
Rev. A | Page 6 of 60 | February 2008
The ADSP-BF539F4 contains a 4M bit (256K
boot sector Spansion S29AL004D known good die flash mem-
ory
bottom boot sector Spansion S29AL008D known good die flash
memory. Features include the following:
The Blackfin processor connects to the flash memory die with
address, data, chip enable, write enable, and output enable con-
trols as if it were an external memory device.
The flash chip enable pin FCE must be connected to AMS0 or
AMS3–1 through a printed circuit board trace. When connected
to AMS0, the Blackfin processor can boot from the flash die.
When connected to AMS3–1, the flash memory will appear as
nonvolatile memory in the processor memory map, shown in
Figure 3 on Page
Flash Memory Programming
The ADSP-BF539F4 and ADSP-BF539F8 flash memory can be
programmed before or after mounting on the printed
circuit board.
To program the flash prior to mounting on the printed circuit
board, use a hardware programming tool that can provide the
data, address, and control stimuli to the flash die through the
external pins on the package. During this programming, V
and GND must be provided to the package and the Blackfin
must be held in reset with bus request (BR) asserted and a
CLKIN provided.
The VisualDSP++
ory after the device is mounted on a printed circuit board.
Flash Memory Sector Protection
To use the sector protection feature, a high voltage (+12 V nom-
inal) must be applied to the flash FRESET pin. Refer to the flash
data sheet for details.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory mapped registers (MMRs) at addresses near the top of the
4G byte address space. These are separated into two smaller
blocks, one of which contains the control MMRs for all core
functions, and the other of which contains the registers needed
for setup and control of the on-chip peripherals outside of the
core. The MMRs are accessible only in supervisor mode and
appear as reserved space to on-chip peripherals.
†
‡
Refer to the Spansion website for the appropriate data sheets.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
• Access times as fast as 70 ns (EBIU registers be set
• Sector protection
• One million write cycles per sector
• 20 year data retention
†
. The ADSP-BF539F8 contains an 8M bit (512K
appropriately)
6.
‡
tools can be used to program the flash mem-
16-bit) bottom
16-bit)
DDEXT