adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 11

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

2-WIRE INTERFACE
The ADSP-BF539/ADSP-BF539F processors incorporate two
2-wire interface (TWI) modules that are compatible with the
Philips Inter-IC bus standard. The TWI modules offer the capa-
bilities of simultaneous master and slave operation, support for
7-bit addressing, and multimedia data arbitration. The TWI also
includes master clock synchronization and support for clock
low extension.
The TWI interface uses two pins for transferring clock (SCLx)
and data (SDAx) and supports the protocol at speeds up to
400 kbps.
The TWI interface pins are compatible with 5 V logic levels.
UART PORTS
The ADSP-BF539/ADSP-BF539F processor incorporates three
full-duplex universal asynchronous receiver/transmitter
(UART) ports, which are fully compatible with PC standard
UARTs. The UART ports provide a simplified UART interface
to other peripherals or hosts, supporting full-duplex, DMA sup-
ported, asynchronous transfers of serial data. The UART ports
include support for 5 data bits to 8 data bits, 1-stop bit or 2-stop
bits, and none, even, or odd parity. The UART ports support
two modes of operation:
Each UART port’s baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
Each UART port’s clock rate is calculated as:
where the 16-bit UART_Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits).
In conjunction with the general-purpose timer functions, auto-
baud detection is supported on UART0.
The capabilities of the UARTs are further extended with sup-
port for the Infrared Data Association (IrDA
Physical Layer Link Specification (SIR) protocol.
• PIO (programmed I/O) – The processor sends or receives
• DMA (direct memory access) – The DMA controller trans-
• Supporting bit rates ranging from (f
• Supporting data formats from 7 bits to 12 bits per frame.
• Both transmit and receive operations can be configured to
data by writing or reading I/O mapped UART registers.
The data is double buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
(f
generate maskable interrupts to the processor.
SCLK
/16) bits per second.
UART Clock Rate
=
---------------------------------------------- -
16 UART_Divisor
×
f
SCLK
SCLK
/1,048,576) to
®
) Serial Infrared
Rev. A | Page 11 of 60 | February 2008
PROGRAMMABLE I/O PINS
The ADSP-BF539/ADSP-BF539F processor has numerous
peripherals that may not all be required for every application.
Many of the pins thus have a secondary function, as program-
mable I/O pins. There are two types of programmable I/O pins
on the ADSP-BF539/ADSP-BF539F processor, with slightly dif-
ferent functionality: programmable flags and general-purpose
I/O.
Programmable Flags (PFx)
The ADSP-BF539/ADSP-BF539F processors have 16 bidirec-
tional, general-purpose programmable flag (PF15–0) pins. Each
programmable flag can be individually controlled by manipula-
tion of the flag control, status, and interrupt registers:
General-Purpose I/O
The ADSP-BF539/ADSP-BF539F processors have 38 general-
purpose I/O pins that are multiplexed with other peripherals.
They are arranged into ports C, D, E, and F as shown in
on Page
that the GPIO pins cannot generate interrupts to the processor.
• Flag direction control register – Specifies the direction of
• Flag control and status registers – The
• Flag interrupt mask registers – The two flag interrupt mask
• Flag interrupt sensitivity registers – The two flag interrupt
each individual PFx pin as input or output.
ADSP-BF539/ADSP-BF539F processors employ a “write
one to modify” mechanism that allows any combination of
individual flags to be modified in a single instruction, with-
out affecting the level of any other flags. Four control
registers are provided. One register is written in order to set
flag values, one register is written in order to clear flag val-
ues, one register is written in order to toggle flag values,
and one register is written in order to specify a flag value.
Reading the flag status register allows software to interro-
gate the sense of the flags.
registers allow each individual PFx pin to function as an
interrupt to the processor. Similar to the two flag control
registers that are used to set and clear individual flag values,
one flag interrupt mask register sets bits to enable interrupt
function, and the other flag interrupt mask register clears
bits to disable interrupt function. PFx pins defined as
inputs can be configured to generate hardware interrupts,
while output PFx pins can be triggered by software
interrupts.
sensitivity registers specify whether individual PFx pins are
level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
12. The GPIO differ from the programmable flags in
ADSP-BF539/ADSP-BF539F
Table 4