adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 32

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adsp-bf539bbcz-5f8

Manufacturer Part Number
adsp-bf539bbcz-5f8
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
ADSP-BF539/ADSP-BF539F
Table 18. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
S = number of programmed setup cycles, RA = number of programmed read access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SDAT
HDAT
DANR
HAA
DO
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
ARE
ARDY
AOE
DATA15–0
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Negated Delay from AMSx Asserted
ARDY Asserted Hold After ARE Negated
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
SETUP
t
DO
Figure 13. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
t
DANR
PROGRAMMED READ ACCESS
t
DO
2
2
Rev. A | Page 32 of 60 | February 2008
4 CYCLES
1
BE, ADDRESS
ACCESS EXTENDED
t
t
HO
SDAT
READ
Min
2.1
0.8
0.0
0.8
1 CYCLE
HOLD
t
HDAT
t
HAA
Max
(S+RA–2)
6.0
t
HO
t
SCLK
ns
Unit
ns
ns
ns
ns
ns

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