adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 52

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
POWER DISSIPATION
Many operating conditions can affect power dissipation. System
designers should refer to Estimating Power for ADSP-
BF538/ADSP-BF539 Blackfin Processors (EE-298) on the Analog
Devices, Inc. website (www.analog.com)—use site search on
“EE-298.” This document provides detailed information for
optimizing your design for lowest power.
See the ADSP-BF539/BF539F Blackfin Processor Hardware Ref-
erence Manual for definitions of the various operating modes
and for instructions on how to minimize system power.
TEST CONDITIONS
All timing parameters appearing in this data sheet were mea-
sured under the conditions described in this section.
shows the measurement point for ac measurements (except out-
put enable/disable). The measurement point V
V
Output Enable Time Measurement
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving.
The output enable time t
a reference signal reaches a high or low voltage level to the point
when the output starts driving as shown on the right side of
ure 41, “Output Enable/Disable,” on Page
The time t
signal switches, to when the output voltage reaches V
or V
V
the output starts driving to when the output reaches the
V
Time t
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time Measurement
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
difference between t
side of
The time for the voltage on the bus to decay by ΔV is dependent
on the capacitive load C
time can be approximated by the equation:
DDEXT
DDEXT
TRIP
TRIP
(high) or V
ENA
Figure
(nominal) = 3.3 V.
OUTPUT
(nominal) = 3.3 V. Time t
(low). V
INPUT
OR
is calculated as shown in the equation:
ENA_MEASURED
Measurements (Except Output Enable/Disable)
41.
t
Figure 40. Voltage Reference Levels for AC
DIS
V
TRIP
MEAS
TRIP
t
ENA
=
(high) is 2.0 V and V
(low) trip voltage.
DIS_MEASURED
t
=
DIS_MEASURED
is the interval, from when the reference
L
ENA
t
and the load current I
ENA_MEASURED
is the interval from the point when
and t
TRIP
–
is the interval from when
DECAY
t
DECAY
TRIP
–
52.
t
TRIP
as shown on the left
(low) is 1.0 V for
MEAS
L
. This decay
Rev. A | Page 52 of 60 | February 2008
is 1.5 V for
V
MEAS
Figure 40
DIS
TRIP
is the
(high)
Fig-
The time t
ΔV equal to 0.5 V for V
The time t
signal switches, to when the output voltage decays ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-BF539/ADSP-BF539F
processor output voltage and the input threshold for the device
requiring the hold time. C
line), and I
line). The hold time will be t
able times as specified in the
(for example t
Table 21 on Page
(MEASURED)
(MEASURED)
t DIS
V OL
V OH
OUTPUT
OUTPUT STOPS DRIVING
Figure 42. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
PIN
TO
DECAY
DIS+_MEASURED
L
is the total leakage or three-state current (per data
DSDAT
DECAY
is calculated with test loads C
t DIS_MEASURED
REFERENCE
35).
V OH (MEASURED) 2 DV
V OL (MEASURED) + DV
Figure 41. Output Enable/Disable
SIGNAL
for an SDRAM write cycle as shown in
t DECAY
using the equation given above. Choose ΔV
t
DECAY
is the interval from when the reference
DDEXT
L
HIGH IMPEDANCE STATE
is the total bus capacitance (per data
DECAY
Timing Specifications on Page 29
30pF
=
(nominal) = 3.3 V.
t ENA
(
C
plus the various output dis-
L
Δ
V
OUTPUT STARTS DRIVING
50
) I
⁄
L
t ENA_MEASURED
V TRIP (LOW)
V TRIP (HIGH)
L
t TRIP
and I
V OH (MEASURED)
V OL (MEASURED)
V
L
LOAD
, and with