adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 44
adsp-bf539bbcz-5f8
Manufacturer Part Number
adsp-bf539bbcz-5f8
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
1.ADSP-BF539BBCZ-5F8.pdf
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ADSP-BF539/ADSP-BF539F
Serial Peripheral Interface Ports — Master Timing
Table 29
Table 29. Serial Peripheral Interface (SPI) Ports—Master Timing
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SDSCIM
SPICHM
SPICLM
SPICLK
HDSM
SPITDM
DDSPIDM
HDSPIDM
and
CPHA=1
CPHA=0
Figure 25
(OUTPUT)
(INPUT)
(INPUT)
SPIxSELy
(OUTPUT)
(OUTPUT)
MISOx
MISOx
(CPOL = 0)
(CPOL = 1)
(OUTPUT)
(OUTPUT)
MOSIx
MOSIx
SCKx
SCKx
Data Input Valid to SCKx Edge (Data Input Setup)
SCKx Sampling Edge to Data Input Invalid
SPIxSELy Low to First SCKx edge
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCKx Edge to SPIxSELy High
Sequential Transfer Delay
SCKx Edge to Data Out Valid (Data Out Delay)
SCKx Edge to Data Out Invalid (Data Out Hold)
describe SPI ports master operations.
t
SSPIDM
t
SDSCIM
MSB VALID
t
SSPIDM
MSB
t
t
SPICHM
SPICLM
Figure 25. Serial Peripheral Interface (SPI) Ports—Master Timing
MSB VALID
t
HSPIDM
t
t
t
DDSPIDM
MSB
SPICLM
SPICHM
Rev. A | Page 44 of 60 | February 2008
t
HSPIDM
t
DDSPIDM
t
HDSPIDM
LSB VALID
t
t
SSPIDM
SPICLK
t
HDSPIDM
LSB VALID
LSB
t
HDSM
LSB
t
HSPIDM
Min
7.5
–1.5
2t
2t
2t
4t
2t
2t
0
–1.0
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
t
SPITDM
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Max
6
+4.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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