adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 33

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adsp-bf539bbcz-5f8

Manufacturer Part Number
adsp-bf539bbcz-5f8
Description
Blackfin Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet
Asynchronous Memory Write Cycle Timing
Table 19
on Page 34
tions for synchronous and for asynchronous ARDY.
Table 19. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SARDY
HARDY
DDAT
ENDAT
DO
HO
ADDR19–1
DATA15–0
and
CLKOUT
ABE1–0
AMSx
ARDY
describe asynchronous memory write cycle opera-
AWE
Table 20 on Page 34
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
DATA15–0 Disable After CLKOUT
DATA15–0 Enable After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
t
ENDAT
SETUP
t
DO
and
t
t
SARDY
DO
Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
WRITE DATA
Figure 14
PROGRAMMED WRITE
ACCESS 2 CYCLES
1
1
BE, ADDRESS
and
Rev. A | Page 33 of 60 | February 2008
Figure 15
t
HARDY
t
SARDY
EXTENDED
ACCESS
1 CYCLE
t
HARDY
t
HO
1 CYCLE
HOLD
t
DDAT
t
HO
ADSP-BF539/ADSP-BF539F
Min
4.0
0.0
1.0
0.8
Max
6.0
6.0
Unit
ns
ns
ns
ns
ns
ns

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