adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 29

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

TIMING SPECIFICATIONS
Table 13
ADSP-BF539/ADSP-BF539F processor clocks. Take care in
selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock, system clock, and voltage-controlled
Table 13. Core Clock (CCLK) Requirements
Table 14. Phase-Locked Loop Operating Conditions
Table 15. System Clock (SCLK) Requirements
1
2
Parameter Description
f
Parameter Description
f
f
f
f
Parameter
f
f
t
Guaranteed to t
VCO
CCLK
CCLK
CCLK
CCLK
SCLK
SCLK
SCLK
(= 1/f
describes the timing requirements for the
SCLK
1
) must be greater than or equal to t
SCLK
Voltage Controlled Oscillator (VCO) Frequency
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
CLK Frequency (V
Description
CLKOUT/SCLK Frequency (V
CLKOUT/SCLK Frequency (V
= 7.5 ns. See
Table 21 on Page
DDINT
DDINT
DDINT
DDINT
= 1.2 V Minimum)
= 1.14 V Minimum)
= 1.045 V Minimum)
= 0.95 V Minimum)
CCLK
35.
DDINT
DDINT
≥ 1.14 V)
< 1.14 V)
Rev. A | Page 29 of 60 | February 2008
oscillator (VCO) operating frequencies, as described in
lute Maximum Ratings on Page
locked loop operating conditions.
requirements.
Internal Regulator
Setting
1.25 V
1.20 V
1.10 V
1.00 V
ADSP-BF539/ADSP-BF539F
Min
50
28.
Table 15
Table 14
Max
Max f
533
500
444
400
Max
Max
133
100
lists system clock
2
describes phase-
CCLK
Unit
MHz
Unit
MHz
MHz
MHz
MHz
Unit
MHz
MHz
Abso-