adsp-bf539bbcz-5f8 Analog Devices, Inc., adsp-bf539bbcz-5f8 Datasheet - Page 10

• Manufacturer Part Number: adsp-bf539bbcz-5f8
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF539/ADSP-BF539F
timer, enables the appropriate interrupt, and then enables the
timer. Thereafter, the software must reload the counter before it
counts to zero from the programmed value. This protects the
system from remaining in an unknown state where software,
which would normally reset the timer, has stopped running due
to an external noise condition or software error.
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF539/ADSP-BF539F pro-
cessor peripherals. After a reset, software can determine if the
watchdog was the source of the hardware reset by interrogating
a status bit in the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of f
TIMERS
There are four general-purpose programmable timer units in
the ADSP-BF539/ADSP-BF539F processors. Three timers have
an external pin that can be configured either as a pulse-width
modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and peri-
ods of external events. These timers can be synchronized to an
external clock input to the PF1 pin (TACLK), an external clock
input to the PPI_CLK pin (TMRCLK), or to the internal SCLK.
The timer units can be used in conjunction with UART0 to
measure the width of the pulses in the data stream to provide an
auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the three general-purpose programmable timers,
a fourth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
SERIAL PORTS (SPORT
The ADSP-BF539/ADSP-BF539F processors incorporate four
dual-channel synchronous serial ports for serial and multipro-
cessor communications. The SPORTs support the following
features:
• I
• Bidirectional operation – Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports – Each port
• Clocking – Each transmit and receive port can either use an
• Word length – Each SPORT supports serial data words
pendent transmit and receive pins, enabling 16 channels of
I
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
external serial clock or generate its own, in frequencies
ranging from (f
from 3 bits to 32 bits in length, transferred most significant
bit first or least significant bit first.
2
2
S capable operation.
S stereo audio.
SCLK
.
SCLK
/131,070) Hz to (f
s
)
SCLK
/2) Hz.
Rev. A | Page 10 of 60 | February 2008
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The ADSP-BF539/ADSP-BF539F processors incorporate three
SPI-compatible ports that enable the processor to communicate
with multiple SPI compatible devices.
The SPI interface uses three pins for transferring data: two data
pins (master output-slave input, MOSIx, and master input-slave
output, MISOx) and a clock pin (serial clock, SCKx). An SPI
chip select input pin (SPIxSS) lets other SPI devices select the
processor. For SPI0, seven SPI chip select output pins
(SPI0SEL7–1) let the processor select other SPI devices. SPI1
and SPI2 each have a single SPI chip select output pin
(SPI1SEL1 and SPI2SEL1) for SPI point-to-point communica-
tion. Each of the SPI select pins is a reconfigured GPIO pin.
Using these pins, the SPI ports provide a full-duplex, synchro-
nous serial interface, which supports both master/slave modes
and multimaster environments.
The SPI ports’ baud rate and clock phase/polarities are pro-
grammable, and they each have an integrated DMA controller,
configurable to support transmit or receive data streams. Each
SPI DMA controller can only service unidirectional accesses at
any given time.
The SPI port clock rate is calculated as:
where the 16-bit SPIx_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
• Framing – Each transmit and receive port can run with or
• Companding in hardware – Each SPORT can perform
• DMA operations with single-cycle overhead – Each SPORT
• Interrupts – Each transmit and receive port generates an
• Multichannel capability – Each SPORT supports 128 chan-
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SPI Clock Rate
=
-------------------------------------- -
2
×
SPIx_BAUD
f
SCLK