adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 9

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

support for 5 to 8 data bits; 1 or 2 stop bits; and none, even,
or odd parity. The UART port supports two modes of
operation:
• PIO (Programmed I/O) – The processor sends or receives
• DMA (Direct Memory Access) – The DMA controller
The UART port's baud rate (see
format, error code generation and status, and interrupts are
programmable:
• Supporting bit rates ranging from (f
• Supporting data formats from 7 to12 bits per frame.
• Both transmit and receive operations can be configured
Figure 4. UART Clock Rate Calculation
1
In conjunction with the general-purpose timer functions,
autobaud detection is supported.
The capabilities of the UART are further extended with
support for the Infrared Data Association (IrDA®) Serial
Infrared Physical Layer Link Specification (SIR) protocol.
Programmable Flags (PFx)
The ADSP-21532 has 16 bi-directional, general-purpose
Programmable Flag (PF15–0) pins. Each programmable
flag can be individually controlled by manipulation of the
flag control, status and interrupt registers:
• Flag Direction Control Register – Specifies the direction
• Flag Control and Status Registers – The ADSP-21532
Where D = 1 to 65536
September 2001
data by writing or reading I/O-mapped UATX or UARX
registers, respectively. The data is double-buffered on
both transmit and receive.
transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
DMA channels, one for transmit and one for receive.
These DMA channels have lower priority than most
DMA channels because of their relatively low service
rates.
(f
to generate maskable interrupts to the processor.
of each individual PFx pin as input or output.
employs a “write one to modify” mechanism that allows
any combination of individual flags to be modified in a
single instruction, without affecting the level of any other
flags. Four control registers are provided. One register is
written in order to set flag values, one register is written
in order to clear flag values, one register is written in order
REV. PrA
SCLK
/16) bits per second.
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
UART Clock Rate
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
Figure
=
---------------- -
16 D
f
SCLK
SCLK
×
1
4), serial data
/ 1048576) to
• Flag Interrupt Mask Registers – The two Flag Interrupt
• Flag Interrupt Sensitivity Registers – The two Flag
Parallel Peripheral Interface
The ADSP-21532 provides a Parallel Peripheral Interface
(PPI) that can connect directly to parallel A/D and D/A
converters, video encoders and decoders, and other general-
purpose peripherals. The PPI has a dedicated clock pin and
five dedicated data pins. Up to 11 additional data pins are
available by re-configuring programmable flag pins. An
additional PF pin is available as a Frame Sync signal.
The PPI supports two operating modes: general purpose
mode and CCIR 656 mode. In general-purpose mode, the
PPI provides:
• Half-duplex, bi-directional data transfer with up to 16 bits
• Shared PPI pins are configurable as a PF or PPI pins.
• Frame sync controls DMA transfer.
In CCIR 656 mode, the PPI provides:
• Half-duplex, bi-directional data transfer with up to 10 bits
• Support for embedded start of line (SOL) and start of
• SOL and SOF syncs control DMA transfer.
• Programmable blanking interval support.
Dynamic Power Management
The ADSP-21532 provides four operating modes, each with
a different performance/power-dissipation profile. In
addition, the Dynamic Power Management provides the
control functions to dynamically alter the processor core
supply voltage, further reducing power dissipation. Control
of clocking to each of the ADSP-21532 peripherals also
reduces power consumption. See
the power settings for each mode.
to toggle flag values, and one register is written in order
to specify a flag value. Reading the flag status register
allows software to interrogate the sense of the flags.
Mask Registers allow each individual PFx pin to function
as an interrupt to the processor. Similar to the two Flag
Control Registers that are used to set and clear individual
flag values, one Flag Interrupt Mask Register sets bits to
enable interrupt function, and the other Flag Interrupt
Mask register clears bits to disable interrupt function.
PFx pins defined as inputs can be configured to generate
hardware interrupts, while output PFx pins can be con-
figured to generate software interrupts.
Interrupt Sensitivity Registers specify whether individual
PFx pins are level- or edge-sensitive and specify—if edge-
sensitive—whether just the rising edge or both the rising
and falling edges of the signal are significant. One register
selects the type of sensitivity, and one register selects
which edges are significant for edge-sensitivity.
of data.
of data.
field (SOF) synchronization pulses.
Table 3
ADSP-21532
for a summary of
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