adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 10

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

ADSP-21532
Full On Operating Mode – Maximum Performance
In the Full On mode, the PLL is enabled, and is not
bypassed, providing the maximum operational frequency.
This is the power-up default execution state in which
maximum performance can be achieved. The processor
core and all enabled peripherals run at full speed.
Active Operating Mode – Moderate Power Savings
In the Active mode, the PLL is bypassed. The input clock
(CLKIN) is used to generate the clocks for the processor
core (CCLK) and peripherals (SCLK). When the PLL is
bypassed, CCLK runs at the CLKIN frequency. Significant
power savings can be achieved in this mode by modifying
the PLL multiplication ratio. To change this ratio, set the
appropriate values in the MSEL fields of the PLL control
register (PLL_CTL). The PLL lock counter (PLL
LOCK_CNT) determines when the new multiplier ratio
takes effect.
When in the Active mode, system DMA access to appropri-
ately configured L1 memory is supported.
Table 3. Power Settings
Sleep Operating Mode – High Power Savings
The Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode.
Typically an external event or RTC activity will wake up the
processor. When in the Sleep mode, assertion of any
interrupt will cause the processor to sense the value of the
bypass bit (BYPASS) in the PLL control register
(PLL_CTL). If bypass is disabled, the processor will tran-
sition to the Full On mode. If bypass is enabled, the
processor will transition to the Active mode.
When in the Sleep mode, system DMA access to L1
memory is not supported.
Deep Sleep Operating Mode – Maximum Power Savings
The Deep Sleep mode maximizes power savings by
disabling the clocks to the processor core (CCLK) and to
all synchronous systems (SCLK). Asynchronous systems,
such as the RTC, may still be running but will not be able
to access internal resources or external memory. This
powered-down mode can only be exited by assertion of the
reset interrupt (RESET) or by an asynchronous interrupt
10
Full On
Active
Sleep
Deep Sleep
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generated by the RTC. When in Deep Sleep mode, assertion
of RESET or the RTC asynchronous interrupt causes the
processor to transition to the Full On mode.
Power Savings
As shown in
different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compli-
ance with industry standards and conventions. By isolating
the internal logic of the ADSP-21532 into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of Dynamic Power Management,
without affecting the RTC or other I/O devices.
Table 4. ADSP-21532 Power Domains
The power dissipated by a processor is largely a function of
the clock frequency of the processor and the square of the
operating voltage. For example, reducing the clock
frequency by 25% results in a 25% reduction in power dis-
sipation, while reducing the voltage by 25% reduces power
dissipation by more than 40%. Further, these power savings
are additive—in that if the clock frequency and power are
both reduced, and the power savings are dramatic.
The Dynamic Power Management feature of the ADSP-
21532 allows both the processor’s input voltage (V
clock frequency (f
As explained above, the savings in power dissipation can be
modeled by the following equations:
where the variables in the equations are:
• f
• f
• V
• V
Voltage Regulation
The ADSP-21532 provides an on-chip voltage regulator
that can generate internal voltage levels from an external
2.25 V to 3.6 V supply. As shown in
external components are required to complete the power
Power Domain
All internal logic, except RTC
RTC internal logic and crystal I/O
All other I/O
CCLKNOM
CCLKRED
Power Savings Factor
% Power Savings
DDINTNOM
DDINTRED
is the reduced core clock frequency
is the nominal core clock frequency
is the reduced internal supply voltage
is the nominal internal supply voltage
Table
CLK
4, the ADSP-21532 supports three
=
) to be dynamically controlled.
(
1 Power Savings Factor
=
–
---------------------------- -
f
f
CCLKNOM
CCLKRED
September 2001
Figure
×


---------------------------------- -
V
V
DDINTNOM
DDINTRED
5, minimal
VDD
Range
V
V
V
) 100%
DDINT
DDRTC
DDEXT
×
DDINT
REV. PrA


) and
2