adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 11

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

management system. The regulator controls the internal
logic voltage levels and is programmable with the Voltage
Regulator Control Register (VRCTL) in increments of
50 mV. The regulator can also be disabled and bypassed at
the user’s discretion.
Figure 5. Voltage Regulator Circuit
Clock Signals
The ADSP-21532 can be clocked by an external crystal
circuit, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
This external clock connects to the DSP's CLKIN pin.
CLKIN input cannot be halted, changed, or operated below
the specified frequency during normal operation. This clock
signal should be a TTL-compatible signal. The DSP
provides a user-programmable 1x to 31x multiplication of
the input clock to support external to internal (DSP core)
clock ratios. The default multiplier is 10x, but can be con-
trolled in software at runtime.
All on-chip peripherals operate at the rate set by the system
clock (SCLK). The system clock frequency is programma-
ble by means of the SSEL3–0 bits of the PLL_DIV register.
The values programmed into the SSEL fields define a divide
ratio between the PLL output (VCO) and the system clock.
SCLK divider values are 1 through 15.
typical system clock ratios:
Table 5. System Clock Ratios
Signal Name
SSEL3–0
0001
0110
1111
September 2001
VREF
REV. PrA
-
+
INTERNAL
CIRCUI T
DSP
Divider
Ratio
VCO/SCLK
1:1
6:1
15:1
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
V
V
D D C TR L
D D IN T
10 µ µ µ µ F
ELECTRO LYTIC
PRELIMINARY TECHNICAL DATA
TANTALUM
OR
Example Frequency Ratios
(MHz)
VCO
100
300
300
For current information contact Analog Devices at 800-262-5643
.1 µ µ µ µ F
CERAMIC
COMPONENTS
EXTERNAL
Table 5
SCLK
100
50
20
2.25V -> 3.6V
illustrates
V
D D EX T
The maximum frequency of the system clock is f
that the divisor ratio must be chosen to limit the system clock
frequency to its maximum of f
changed dynamically without any PLL lock latencies by
writing the appropriate values to the PLL divisor register
(PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL[1:0] bits of the PLL_DIV
register. Supported CCLK divider ratios are 1, 2, 4, and 8
as shown in
bility is useful for fast core frequency modifications.
Table 6. Core Clock Ratios
Booting Modes
The ADSP-21532 has three mechanisms (listed in
for automatically loading internal L1 instruction memory
after a reset. A fourth mode is provided to execute from
external memory, bypassing the boot sequence.
Table 7. Booting Modes
The BMODE pins of the Reset Configuration Register,
sampled during power-on resets and software-initiated
resets, implement the following modes:
Signal Name
CSEL[1:0]
00
01
10
11
BMODE2–0
000
001
010
011
100
101 –111
• Execute from 16-bit external memory – Execution
• Boot from 8-bit external FLASH memory – The 8-bit
starts from address 0x2000000 with 16-bit packing.
The boot ROM is bypassed in this mode.
FLASH boot routine located in boot ROM memory
space is set up using Asynchronous Memory Bank 4.
All configuration settings are set for the slowest device
possible (3-cycle hold time; 15-cycle R/W access times;
4-cycle setup).
Table
Divider
Ratio
VCO/CCLK
1
2
4
8
6. This programmable core clock capa-
Description
Execute from 16-bit external memory
(Bypass Boot ROM)
Boot from 8-bit flash
Boot from SPI0 serial ROM (8-bit
address range)
Boot from SPI0 serial ROM (16-bit
address range)
Boot from internal ROM
Reserved
SCLK
Example Frequency Ratios
VCO
300
300
200
200
. The SSEL value can be
ADSP-21532
CCLK
300
150
50
25
SCLK
Table
. Note
7)
11