adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 8

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

ADSP-21532
• Companding in hardware – Each SPORT can perform
• DMA operations with single-cycle overhead – Each
• Interrupts – Each transmit and receive port generates an
• Multichannel capability – Each SPORT supports 128
Serial Peripheral Interface (SPI) Port
The ADSP-21532 has an SPI-compatible port that enables
the processor to communicate with multiple SPI-compati-
ble devices.
The SPI interface uses three pins for transferring data: two
data pins (Master Output-Slave Input, MOSI, and Master
Input-Slave Output, MISO) and a clock pin (Serial Clock,
SCK). An SPI chip select input pin (SPISS) lets other SPI
devices select the DSP, and seven SPI chip select output
pins (SPISEL7–1) let the DSP select other SPI devices. The
SPI select pins are reconfigured Programmable Flag pins.
Using these pins, the SPI port provides a full duplex, syn-
chronous serial interface, which supports both master/slave
modes and multimaster environments.
The SPI port’s baud rate and clock phase/polarities are pro-
grammable (see
controller, configurable to support transmit or receive data
streams. The SPI’s DMA controller can only service unidi-
rectional accesses at any given time.
Figure 3. SPI Clock Rate Calculation
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
8
A-law or µ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.
SPORT can automatically receive and transmit multiple
buffers of memory data. The DSP can link or chain
sequences of DMA transfers between a SPORT and
memory.
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
channels out of a 1024 channel window and is compatible
with the H.100, H.110, MVIP-90, and HMVIP
standards.
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
SPI Clock Rate
Figure
3), and it has an integrated DMA
PRELIMINARY TECHNICAL DATA
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2
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SPIBAUD
f
SCLK
In master mode, the DSP performs the following sequence
to set up and initiate SPI transfers:
1. Enables and configures the SPI port’s operation (data
2. Selects the target SPI slave with an SPISELx output
3. Defines one or more DMA descriptors in the DSP’s
4. Enables the SPI DMA engine and specifies transfer
5. In non-DMA mode only, reads or writes the SPI port
In slave mode, the DSP performs the following sequence to
set up the SPI port to receive data from a master transmitter:
1. Enables and configures the SPI slave port to match the
2. Defines and generates a receive DMA descriptor in the
3. Enables the SPI DMA engine for a receive access
4. Starts receiving the data on the appropriate SPI SCK
Slave mode transmit operation is similar, except the DSP
specifies the data buffer in memory from which to transmit
data, generates and relinquishes control of the transmit
DMA descriptor, and begins filling the SPI port’s data
buffer. If the SPI controller isn’t ready on time to transmit,
it can transmit a “zero” word.
UART Port
The ADSP-21532 provides a full-duplex Universal Asyn-
chronous Receiver/Transmitter (UART) port, which is fully
compatible with PC-standard UARTs. The UART port
provides a simplified UART interface to other peripherals
or hosts, supporting full-duplex, DMA-supported, asyn-
chronous transfers of serial data. The UART port includes
The SCK line generates the programmed clock pulses for
simultaneously shifting data out on MOSI and shifting
data in on MISO. In DMA mode only, transfers continue
until the SPI DMA word count transitions from 1 to 0.
In DMA mode only, reception continues until the SPI
DMA word count transitions from 1 to 0. DMA can
continue by queuing up the next DMA descriptor.
size, and transfer format).
pin (reconfigured Programmable Flag pin).
memory space (optional in DMA mode only).
direction (optional in DMA mode only).
receive or transmit data buffer.
operation parameters set up on the master (data size
and transfer format) SPI transmitter.
DSP’s memory space to interrupt at the end of the data
transfer (optional in DMA mode only).
(optional in DMA mode only).
edges after receiving an SPI chip select on an SPISS
input pin (reconfigured Programmable Flag pin) from
a master.
September 2001
REV. PrA