adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 14

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

ADSP-21532
Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
JTAG Emulator Pod Connector
Figure 8
at the 14-pin target end.
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Figure 8. JTAG Pod Connector Dimensions
Figure 9. JTAG Pod Connector Keep-Out Area
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website
14
details the dimensions of the JTAG pod connector
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
KEY (NO PIN)
0.15"
BTRST
0.64"
BTMS
BTCK
GND
BTDI
GND
0.88"
Figure 9
TOP VIEW
11
13
PRELIMINARY TECHNICAL DATA
1
3
5
7
9
9
0.24"
For current information contact Analog Devices at 800-262-5643
14
10
12
displays the keep-out area
2
4
6
8
EMU
GND
TMS
TCK
TRST
TDI
TDO
0.10"
(www.analog.com)—use site search on “EE-68”. This
document is updated regularly to keep pace with improve-
ments to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-
21532 architecture and functionality. For additional infor-
mation on the Blackfin DSP Family core architecture and
instruction set, see the Analog Devices’ website.
PIN DESCRIPTIONS
ADSP-21532 pin definitions are listed in
following pins are asynchronous: ARDY, PF15–0, NMI,
TRST, RESET, CLKIN, XTAL.
Unused inputs should be tied or pulled to V
The following symbols appear in the Type column of
Table
Power, and G = Ground.
Table 8. Pin Descriptions
Pin Name
Memory Interface
A[19:1]
D[15:0]
ABE
BR
BG
BGH
Asynchronous
Memory Control
AMS3–0
ARDY
AOE
ARE
AWE
Synchronous
Memory Control
SRAS
SCAS
SWE
SCKE
CLKOUT
SA10
SMS
Timers
TMR0
TMR1
TMR2
/SDQM[1:0]
8: I = Input, O = Output, T = Three-State, P =
I/O
I/O
O
O
I
O
O
O
I
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
Function
Address Bus for Async/Sync
Access
Data Bus for Async/Sync
Access
Byte Enables/Data Masks for
Async/Sync Access
Bus Request
Bus Grant
Bus Grant Hang
Bank Select
Hardware Ready Control
Output Enable
Read Enable
Write Enable
Row Address Strobe
Column Address Strobe
Write Enable
Clock Enable
Clock Output
A10 Pin
Bank Select
Timer 0
Timer 1
Timer 2
September 2001
Table
DDEXT
8. The
or GND.
REV. PrA