adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 6

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

ADSP-21532
Event Control
The ADSP-21532 provides the user with a very flexible
mechanism to control the processing of events. In the CEC,
three registers are used to coordinate and control events.
Each register is 16 bits wide:
• CEC Interrupt Latch Register (ILAT) – The ILAT
• CEC Interrupt Mask Register (IMASK) – The IMASK
• CEC Interrupt Pending Register (IPEND) – The IPEND
The SIC allows further control of event processing by
providing three 32-bit interrupt control and status registers.
Each register contains a bit corresponding to each of the
peripheral interrupt events shown in
• SIC Interrupt Mask Register (SIC_IMASK)– This
• SIC Interrupt Status Register (SIC_ISR) – As multiple
• SIC Interrupt Wakeup Enable Register (SIC_IWR) – By
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register indicates when events have been latched. The
appropriate bit is set when the processor has latched the
event and cleared when the event has been accepted into
the system. This register is updated automatically by the
controller, but it may be written only when its correspond-
ing IMASK bit is cleared.
register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event
is unmasked and will be processed by the system when
asserted. A cleared bit in the IMASK register masks the
event, preventing the processor from servicing the event
even though the event may be latched in the ILAT register.
This register may be read or written while in supervisor
mode. (Note that general-purpose interrupts can be
globally enabled and disabled with the STI and CLI
instructions, respectively.)
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automati-
cally by the controller but may be read while in supervisor
mode.
register controls the masking and unmasking of each
peripheral interrupt event. When a bit is set in the register,
that peripheral event is unmasked and will be processed
by the system when asserted. A cleared bit in the register
masks the peripheral event, preventing the processor from
servicing the event.
peripherals can be mapped to a single event, this register
allows the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit
indicates the peripheral is not asserting the event.
enabling the corresponding bit in this register, each
peripheral can be configured to wake up the processor,
should the processor be in a sleep (powered-down) mode
when the event is generated.
“Dynamic Power Management” on page
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
PRELIMINARY TECHNICAL DATA
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Table 2 on page
9.)
5.
Because multiple interrupt sources can map to a single
general-purpose interrupt, multiple pulse assertions can
occur simultaneously, before or during interrupt processing
for an interrupt event already detected on this interrupt
input. The IPEND register contents are monitored by the
SIC as the interrupt acknowledgement.
The appropriate ILAT register bit is set when an interrupt
rising edge is detected (detection requires two processor
clock cycles). The bit is cleared when the respective IPEND
register bit is set. The IPEND bit indicates that the event
has entered into the processor pipeline. At this point the
CEC will recognize and queue the next rising edge event on
the corresponding event input. The minimum latency from
the rising edge transition of the general-purpose interrupt
to the IPEND output asserted is three processor clock
cycles; however, the latency can be much higher, depending
on the activity within and the mode of the processor.
DMA Controllers
The ADSP-21532 has multiple, independent DMA con-
trollers that support automated data transfers with minimal
overhead for the DSP core. DMA transfers can occur
between the ADSP-21532's internal memories and any of
its DMA-capable peripherals. Additionally, DMA transfers
can be accomplished between any of the DMA-capable
peripherals and external devices connected to the external
memory interfaces, including the SDRAM controller, the
asynchronous memory controller and the parallel peripheral
interface. DMA-capable peripherals include the SPORTs,
SPI port, UART, and PPI. Each individual DMA-capable
peripheral has at least one dedicated DMA channel.
The ADSP-21532 DMA controller supports both 1-dimen-
sional (1D) and 2-dimensional (2D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
The 2D DMA supports arbitrary row and column sizes up
to 64Kbytes by 64Kbytes and arbitrary X-, Y-modify values
up to 32KBytes. In addition, the 2D capability supports
interleaved data streams. This feature is especially useful in
video applications where data rates can be reduced by only
transferring active video.
Examples of DMA types supported by the ADSP-21532
DMA controller include:
• Single, linear buffer that stops upon completion
• Circular, auto-refreshing buffer that interrupts on each
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors specifying only
In addition to the dedicated peripheral DMA channels,
there is a separate memory DMA channel provided for
transfers between the various memories of the ADSP-21532
system. This enables transfers of blocks of data between any
full or fractionally full buffer
the base DMA address within a common page
September 2001
REV. PrA