adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 3

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

The 40-bit shifter can perform shifts and rotates and is used
to support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction exe-
cution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative
and indirect conditional jumps (with static branch predic-
tion), and subroutine calls. Hardware is provided to support
Figure 1. MSA DSP Core
Blackfin DSPs support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1
(L1) memories are those that typically operate at the full
processor speed with little or no latency. At the L1 level, the
instruction memory holds instructions only. The two data
memories hold data, and a dedicated scratchpad data
memory stores stack and local variable information.
In addition, multiple L1 memory blocks are provided,
offering a configurable mix of SRAM and cache. The
Memory Management Unit (MMU) provides memory pro-
tection for individual tasks that may be operating on the core
and can protect system registers from unintended access.
The architecture provides three modes of operation: user
mode, supervisor mode, and emulation mode. User mode
has restricted access to certain system resources, thus
September 2001
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
SP
P5
P3
P2
P1
P0
R1
R0
FP
P4
R7
R6
R 5
R 4
R3
R2
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at 800-262-5643
SHIF TER
I 3
BA RREL
I 2
I 1
I0
8
L 3
L2
L1
L 0
AD DR ES S ARI T HMET I C U NI T
DA TA AR I TH MET I C UN I T
A0
16
B 3
B2
B1
B 0
40
M3
M2
M1
M 0
8
8
zero-overhead looping. The architecture is fully interlocked,
meaning that there are no visible pipeline effects when
executing instructions with data dependencies.
The address arithmetic unit provides two addresses for
simultaneous dual fetches from memory. The unit contains
a multiported register file consisting of four sets of 32-bit
Index, Modify, Length, and Base registers (for circular buff-
ering), and eight additional 32-bit pointer registers (for C-
style indexed stack manipulation).
providing a protected software environment, while supervi-
sor mode has unrestricted access to the system and core
resources.
The Blackfin DSP instruction set has been optimized so that
16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, repre-
senting fully featured multifunction instructions. Blackfin
DSPs support a limited multi-issue capability, where a
32-bit instruction can be issued in parallel with two 16-bit
instructions, allowing the programmer to use many of the
core resources in a single instruction cycle.
The Blackfin DSP assembly language uses an algebraic
syntax for ease of coding and readability. The architecture
has been optimized for use in conjunction with the C-
compiler, resulting in fast and efficient software
implementations.
DA G 0
1 6
A1
40
DA G1
8
L OO P BU FFE R
SEQ UEN CER
CONT ROL
D ECO D E
ALI G N
UN I T
ADSP-21532
3