adsp-21532 ETC-unknow, adsp-21532 Datasheet - Page 7

• Manufacturer Part Number: adsp-21532
• Description: Blackfin Dsp
• Manufacturer: ETC-unknow

of the memories—including external SDRAM, ROM,
SRAM, and flash memory—with minimal processor
intervention.
Real-Time Clock
The ADSP-21532 Real-Time Clock (RTC) provides a
robust set of digital watch features, including current time,
stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-21532. The RTC
peripheral has dedicated power supply pins, so that it can
remain powered up and clocked even when the rest of the
processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per
second, minute, hour, or day clock ticks, interrupt on pro-
grammable stopwatch countdown, or interrupt at a
programmed alarm time.
The 32.768 KHz input clock frequency is divided down to
a 1 Hz signal by a prescaler. The counter function of the
timer consists of four counters: a 60-second counter, a
60-minute counter, a 24-hour counter, and an 365-day
counter.
When enabled, the alarm function generates an interrupt
when the output of the timer matches the programmed value
in the alarm control register. There are two alarms: The first
alarm is for a time of day. The second alarm is for a day and
time of that day.
The stopwatch function counts down from a programmed
value, with one-minute resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is
generated.
Like the other peripherals, the RTC can wake up the ADSP-
21532 processor from a low-power state upon generation of
any RTC interrupt.
Watchdog Timer
The ADSP-21532 includes a 32-bit timer, which can be
used to implement a software watchdog function. A
software watchdog can improve system availability by
forcing the processor to a known state through generation
of a hardware reset, non-maskable interrupt (NMI), or
general-purpose interrupt, if the timer expires before being
reset by software. The programmer initializes the count
value of the timer, enables the appropriate interrupt, then
enables the timer. Thereafter, the software must reload the
counter before it counts to zero from the programmed value.
This protects the system from remaining in an unknown
state where software, which would normally reset the timer,
has stopped running due to an external noise condition or
software error.
If configured to generate a hardware reset, the timer can be
programmed to reset only the ADSP-21532 CPU, or both
the CPU and the ADSP-21532 peripherals. After a reset,
software can determine if the watchdog was the source of
September 2001
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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the hardware reset by interrogating a status bit in the timer
control register, which is set only upon a watchdog-
generated reset.
The timer is clocked by the system clock (SCLK), at a
maximum frequency of f
Timers
There are four general-purpose programmable timer units
in the ADSP-21532. Three timers have an external pin that
can be configured either as a Pulse Width Modulator
(PWM) or timer output, as an input to clock the timer, or
as a mechanism for measuring pulse widths of external
events. These timers can be synchronized to an external
clock input or to each other.
The timer units can be used in conjunction with the UART
to measure the width of the pulses in the data stream to
provide an auto-baud detect function for a serial channel.
The timers can generate interrupts to the processor core
providing periodic events for synchronization, either to the
processor clock or to a count of external signals.
In addition to the three general-purpose programmable
timers, a fourth timer is also provided. This extra timer is
clocked by the internal processor clock and is typically used
as a system tick clock for generation of operating system
periodic interrupts.
Serial Ports (SPORTs)
The ADSP-21532 incorporates two dual-channel synchro-
nous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the
following features:
• I
• Bidirectional operation – Each SPORT has two sets of
• Buffered (8-deep) transmit and receive ports – Each port
• Clocking – Each transmit and receive port can either use
• Word length – Each SPORT supports serial data words
• Framing – Each transmit and receive port can run with
independent transmit and receive pins, enabling eight
channels of I
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
an external serial clock or generate its own, in frequencies
ranging from (f
from 3 to 32 bits in length, transferred most significant
bit first.
or without frame sync signals for each data word. Frame
sync signals can be generated internally or externally,
active high or low, and with either of two pulsewidths and
early or late frame sync.
2
S capable operation.
2
S stereo audio.
SCLK
/131070) Hz to (f
SCLK
.
ADSP-21532
SCLK
/2) Hz.
7