dac1205d750 NXP Semiconductors, dac1205d750 Datasheet - Page 24

• Manufacturer Part Number: dac1205d750
• Description: Dac1205d750 Dual 12-bit Dac, Up To 750 Msps; 4? And 8? Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1205D750
Product data sheet
10.4 Input clock
10.5 Timing
The DAC1205D750 can operate at the following clock frequencies:
The input clock is LVDS compliant (see
differential sine wave signal (see
The DAC1205D750 can operate at a sampling frequency (f
data rate (f
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in
when internal PLL bypassed
Fig 8.
Fig 9.
PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off: up to 750 MHz
LVDS clock configuration
Interfacing CML to LVDS
data
) up to 185 MHz. When using the internal PLL, the input data is referenced
All information provided in this document is subject to legal disclaimers.
L
Rev. 2 — 10 September 2010
Z
diff = 100 Ω
LVDS
Dual 12-bit DAC, up to 750 Msps; 4× and 8× interpolating
(off)”.
Z
diff
Figure
= 100 Ω
100 Ω
100 nF
100 nF
V
DDA(1V8)
AGND
Figure
9).
1.1 kΩ
2.2 kΩ
100 Ω
CLKN
CLKP
55 Ω
55 Ω
8) but it can also be interfaced with CML
100 nF
CLKN
CLKP
001aah021
Figure 10 “Input timing diagram
LVDS
s
DAC1205D750
) up to 750 Msps with an input
001aah020
LVDS
© NXP B.V. 2010. All rights reserved.
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