dac1205d750 NXP Semiconductors, dac1205d750 Datasheet
dac1205d750
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dac1205d750 Summary of contents
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... Thanks to its digital on-chip modulation, the DAC1205D750 allows the complex I and Q inputs to be converted from BaseBand (BB) to IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register ...
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... Dual 12-bit DAC 750 Msps; 4× and 8× interpolating Description plastic thermal enhanced thin quad flat package; 100 leads; body 14 × 14 × 1 mm; exposed die pad All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Version SOT638-1 © NXP B.V. 2010. All rights reserved ...
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... SDO 62 DAC1205D750 18 to 25, FIR1 FIR2 LATCH I0 to I11 × 2 × dual port/ interleaved data modes FIR1 FIR2 41, 42, LATCH × 2 × Q11 12 8 CLKP CLOCK GENERATOR/PLL 9 CLKN 66 RESET_N SYNCP Fig 1. Block diagram SCS_N SDIO SCLK ...
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... Fig 2. Pin configuration DAC1205D750 Product data sheet Dual 12-bit DAC 750 Msps; 4× and 8× interpolating DAC1205D750HW AGND All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 75 V DDA(3V3) 74 AUXBP 73 AUXBN 72 AGND 71 V DDA(1V8) ...
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... P digital supply voltage 1 digital ground 38 - test mode 2 (to connect to DGND digital ground All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 © NXP B.V. 2010. All rights reserved ...
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... P analog supply voltage 3 analog ground 77 P analog supply voltage 1 analog ground 79 P analog supply voltage 1 analog ground All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 © NXP B.V. 2010. All rights reserved ...
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... analog ground 97 P analog supply voltage 1 analog ground 99 P analog supply voltage 1.8 V 100 G analog ground [ analog ground All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 © NXP B.V. 2010. All rights reserved ...
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... SCS_N and RESET_N referenced to GNDIO pins IOUTAP, IOUTAN, IOUTBP, IOUTBN, AUXAP, AUXAN, AUXBP and AUXBN referenced to pin AGND pins SYNCP and SYNCN referenced to pin AGND All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Min Max −0.5 +4.6 −0.5 +4.6 −0.5 +3.0 − ...
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... NCO on; all 8× interpolation NCO on I Power-down mode: full power-down; I all V DD DAC A and DAC B I Sleep mode; NCO on All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Ω differential mA; PLL off unless O(fs) Min Typ Max 3.0 3.3 3.6 3.0 3.3 3.6 1.7 1.8 1 ...
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... V IH register value = 00h default register compliance range = 25 °C T amb external voltage 1. differential outputs compliance range All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Ω differential mA; PLL off unless L O(fs) [1] Test Min Typ [3] C 825 - − ...
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... MHz; 0 dBFS 184.32 MHz data MHz 100 MHz MHz; 8-tone; C 500 kHz spacing All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Ω differential mA; PLL off unless O(fs) Min Typ Max - - 185 ...
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... Msps data MHz; 0 dBFS 153.6 MHz dBFS 153.6 MHz −10 dBFS Figure 8). All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Ω differential mA; PLL off unless O(fs) [1] Min Typ Max [ [ [4] - ...
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... NXP Semiconductors 10. Application information 10.1 General description The DAC1205D750 is a dual 12-bit DAC which operates 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 6-bit binary weighted sub-DAC. The input data rate 185 MHz combined with the maximum output sampling rate of 750 Msps make the DAC1205D750 extremely flexible in wide bandwidth and multi-carrier systems. The device’ ...
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... Table 9 “Register allocation t w(RESET_N su(SCS_N SCLK 50 % SDIO h(SDIO) t su(SDIO) SPI timing diagram All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Number of bytes 1 byte transferred 2 bytes transferred 3 bytes transferred 4 bytes transferred map” ...
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... SPI timing characteristics Parameter SCLK frequency SCLK pulse width SCS_N set-up time SCS_N hold time SDIO set-up time SDIO hold time RESET_N pulse width All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Table 8. Min Typ Max - - ...
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Table 9. Register allocation map Address Register name R/W Bit definition Dec Hex Bit 7 0 00h COMMon R/W 3W_SPI 1 01h TXCFG R/W NCO_ON 2 02h PLLCFG R/W PLL_PD 3 03h FREQNCO_LSB R/W 4 04h FREQNCO_LISB R/W 5 05h ...
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... R/W GAP_PD R/W TXCFG register (address 01h) bit description Access Value Description R/W R/W R/W All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 serial interface bus type 0 4 wire SPI 1 3 wire SPI serial interface reset 0 no reset 1 performs a reset on all registers except 00h ...
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... R/W DAC_CLK_POL R/W FREQNCO_LSB register (address 03h) bit description Symbol Access Value Description R/W All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 …continued modulation 000 dual DAC: no modulation 001 positive upper single sideband up-conversion 010 positive lower single sideband up-conversion ...
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... Symbol Access Value Description R/W COARSE[1:0] R/W FINE[5:0] All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 - lower intermediate 8 bits for the NCO frequency setting - upper intermediate 8 bits for the NCO frequency setting - most significant 8 bits for the NCO frequency ...
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... DAC_Cfg register (address 0Fh) bit description Symbol Access Value - MINUS_3DB R/W NOISE_SHPER R/W All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Description - most significant 2 bits for the DAC A gain setting for coarse adjustment - most significant 6 bits for the DAC A offset DAC B power 0 on ...
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... DAC_B_Aux_MSB register (address 1Ch) bit description Symbol Access Value R/W DAC_B_Aux_LSB register (address 1Dh) bit description Symbol Access Value AUX_B_PD R AUX_B[1:0] R/W All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Description f divided SYNC selection 0 disabled 1 enabled - ...
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... Msps Table 31. Address Dec 10.3 Input data The setting applied to MODE_SEL (register 00h[3]; see whether the DAC1205D750 operates in the Dual-port mode or in Interleaved mode (see Table 32). Table 32. Bit 3 setting 0 1 10.3.1 Dual-port mode The data input for Dual-port mode operation is shown in DAC has its own independent data input ...
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... CLK dig Latch I output Latch Q output CLK = internal digital clock dig Interleaved mode timing (8x interpolation, latch on rising edge) All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 FIR 1 FIR 2 FIR 3 2 × 2 × 2 × FIR 1 FIR 2 FIR 3 2 × ...
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... NXP Semiconductors 10.4 Input clock The DAC1205D750 can operate at the following clock frequencies: PLL on 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off 750 MHz The input clock is LVDS compliant (see differential sine wave signal (see Fig 8. ...
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... Dec 2 10.6 FIR filters The DAC1205D750 integrates three selectable Finite Impulse Response (FIR) filters which enables the device to use 4× or 8× interpolation rates. All three interpolation filters have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than 0.0005 dB. The coefficients of the interpolation filters are given in filter coefficients” ...
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... H(44) 0 H(12) −408 H(43) - H(42 H(41) 650 - H(40 −1003 H(39) - H(38 H(37) 1521 - H(36 −2315 H(35) - H(34 H(33) 3671 - H(32 −6642 H(31) - H(30 H(29) 20756 - 32768 - All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 Third interpolation filter Upper Value Lower −2 H(23) H(1) H(22) 0 H(2) H(21) 17 H(3) H(20) 0 H(4) −75 H(19) H(5) H(18) 0 H(6) H(17) 238 H(7) H(16) 0 H(8) −660 H(15) - H(14 H(13) 2530 - - 4096 - - - - - - - - - - - - ...
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... Dual 12-bit DAC 750 Msps; 4× and 8× interpolating × -------------- 32 2 × -------------- 5 2 Table 37 “Inversion filter Inversion filter coefficients Upper H(9) H(8) H(7) H(6) - All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 coefficients”. Value 2 −4 10 −35 401 (1) (2) © NXP B.V. 2010. All rights reserved ...
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... O fs The output current depends on the digital input data: I IOUTP I IOUTN The setting applied to CODING (register 00h[2]; see defines whether the DAC1205D750 operates with a binary input or a two’s complement input. Table 38 “DAC transfer function” when I O(fs) Table 38. Data 0 ... ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 REF. BANDGAP GAPOUT DAC VIRES CURRENT SOURCES ARRAY 001aaj816 Table 20 “DAC_A_Cfg_2 and Table 21 “DAC_A_Cfg_3 register (address Table 23 “DAC_B_Cfg_2 and Table 24 “ ...
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... The coding of the fine gain adjustment is two’s complement. 10.11 Digital offset adjustment When the DAC1205D750 analog output is DC connected to the next stage, the digital offset correction can be used to adjust the common mode level at the output of the DAC. It adds an offset at the end of the digital part, just before the DAC. ...
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... Analog output The DAC1205D750 has two output channels each of which produces two complementary current outputs. These allow the even-order harmonics and noise to be reduced. The pins are IOUTAP/IOUTAN and IOUTBP/IOUTBN, respectively and need to be connected via a load resistor R ...
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... NXP Semiconductors 10.13 Auxiliary DACs The DAC1205D750 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground AUX The output current depends on the auxiliary DAC data: ...
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... DC interface to an Analog Quadrature Modulator (AQM) When the system operation requires to keep the DC component of the spectrum, the DAC1205D750 can use a DC interface to connect to an AQM. In this case, the offset compensation for LO cancellation can be made with the use of the digital offset control in the DAC ...
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... BBP/BBN 1 i(cm) provides an example interface with the auxiliary DACs to an AQM with common mode input level. I(cm) All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 5 V AQM (V i(cm) (2) 750 Ω 750 Ω 237 Ω BBP 237 Ω ...
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... DACs, the input common mode level of the AQM, and the range of offset correction. 10.14.3 AC interface to an Analog Quadrature Modulator (AQM) When the AQM common mode voltage is close to ground, the DAC1205D750 must be AC-coupled and the auxiliary DACs are needed for offset correction. Figure 19 mode input level using auxiliary DACs ...
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... All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 5 V AQM (V = 0.5 V) i(cm) (2) 2 kΩ ...
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... scale (1) ( 0.20 14.1 7.1 14.1 7.1 0.5 0.09 13.9 6.1 13.9 6.1 REFERENCES JEDEC JEITA MS-026 All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 detail 16.15 16.15 0.75 1 0.2 0.08 0.08 15.85 15.85 0.45 EUROPEAN PROJECTION SOT638 θ ...
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... Serial Peripheral Interface Time Division-Synchronous Code Division Multiple Access Upper Intermediate Significant Byte Wideband Code Division Multiple Access Worldwide Interoperability for Microwave Access All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 © NXP B.V. 2010. All rights reserved ...
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... RMS value of the noise, including the harmonics given bandwidth centered around f 14. Revision history Table 44. Revision history Document ID DAC1205D750 v.2 Modifications: DAC1205D750 v.1 DAC1205D750 Product data sheet Dual 12-bit DAC 750 Msps; 4× and 8× interpolating ...
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... Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors’ product specifications. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 2 — 10 September 2010 DAC1205D750 © NXP B.V. 2010. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com DAC1205D750 All rights reserved. Date of release: 10 September 2010 Document identifier: DAC1205D750 ...