dac1205d750 NXP Semiconductors, dac1205d750 Datasheet - Page 18

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dac1205d750

Manufacturer Part Number
dac1205d750
Description
Dac1205d750 Dual 12-bit Dac, Up To 750 Msps; 4? And 8? Interpolating
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
DAC1205D750
Product data sheet
Table 11.
Default settings are shown highlighted.
Table 12.
Default settings are shown highlighted.
Table 13.
Bit
4 to 2 MODULATION[2:0]
1 to 0 INTERPOLATION[1:0]
Bit
7
6
5
4 to 3 PLL_DIV[1:0]
2 to 1 DAC_CLK_DELAY[1:0] R/W
0
Bit
7 to 0 FREQ_NCO[7:0]
Symbol
Symbol
PLL_PD
-
PLL_DIV_PD
DAC_CLK_POL
Symbol
TXCFG register (address 01h) bit description
PLLCFG register (address 02h) bit description
FREQNCO_LSB register (address 03h) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 September 2010
Dual 12-bit DAC, up to 750 Msps; 4× and 8× interpolating
Access Value Description
R/W
R/W
Access Value Description
R/W
-
R/W
R/W
R/W
Access Value Description
R/W
000
001
010
011
100
01
10
11
0
1
reserved
0
1
00
01
10
11
00
01
10
0
1
-
modulation
interpolation
PLL ON
PLL
PLL divider
PLL divider factor
clock edge of DAC (f
phase shift (f
lower 8 bits for the NCO frequency setting
dual DAC: no modulation
positive upper single sideband
up-conversion
positive lower single sideband up-conversion
negative upper single sideband
up-conversion
negative lower single sideband
up-conversion
reserved
switched on
switched off
switched on
switched off
2
4
8
X
120°
240°
normal
inverted
…continued
s
)
DAC1205D750
s
)
undefined
Digital clock delay
undefined
PLL OFF
undefined
X
X
130 ps
280 ps
430 ps
580 ps
X
X
X
X
X
© NXP B.V. 2010. All rights reserved.
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