upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 509

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Main clock
Subsystem
clock
Main clock
Subsystem
clock
Main clock OSTC:
Ring-OSC RCM: Ring-
Function
−
PCC:
Processor clock
control register
(PCC)
OSC mode
register
MCM: Main
clock mode
register
MOC: Main
OSC control
register
Oscillation
stabilization
time counter
status register
Details of
Function
Be sure to clear bit 3 to 0.
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before
setting RSTOP.
When Ring-OSC clock is selected as the clock to be supplied to the CPU, the
divided clock of the Ring-OSC oscillator output (f
hardware (f
Operation of the peripheral hardware with Ring-OSC clock cannot be guaranteed.
Therefore, when Ring-OSC clock is selected as the clock supplied to the CPU, do
not use peripheral hardware. In addition, stop the peripheral hardware before
switching the clock supplied to the CPU from the X1 input clock to the Ring-OSC
clock. Note, however, that the following peripheral hardware can be used when
the CPU operates on the Ring-OSC clock.
• Watchdog timer
• Clock monitor
• 8-bit timer H1 when f
• Peripheral hardware selecting external clock as the clock source
(Except when external count clock of TM00 is selected (TI000 valid edge))
Set MCS = 1 and MCM0 = 1 before switching subsystem clock operation to X1
input clock operation (bit 4 (CSS) of the processor clock control register (PCC) is
changed from 1 to 0).
Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before
setting MSTOP.
To stop X1 oscillation when the CPU is operating on the subsystem clock, set bit 7
(MCC) of the processor clock control register (PCC) to 1 (setting by MSTOP is not
possible).
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
If the STOP mode is entered and then released while the Ring-OSC clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts (“a” below) regardless of whether STOP
mode is released by RESET input or interrupt generation.
OSTS
APPENDIX D LIST OF CAUTIONS
X
= 240 kHz (TYP.)).
User’s Manual U16227EJ3V0UD
R
/2
7
is selected as count clock
Cautions
X
) is supplied to the peripheral
p. 103
p. 104
p. 105
p. 105
p. 106
p. 106
p. 107
p. 107
p. 107
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