upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 103

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Notes 1.
Caution Be sure to clear bit 3 to 0.
Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)
Address: FFFBH
Symbol
PCC
2.
3.
4.
5.
2. f
3. f
4. f
5. f
Bit 5 is read-only.
When the CPU is operating on the subsystem clock, MCC should be used to stop the X1 oscillator
operation. When the CPU is operating on the Ring-OSC clock, use bit 7 (MSTOP) of the main OSC
control register (MOC) to stop the X1 oscillator operation (this cannot be set by MCC). A STOP
instruction should not be used.
Clear this bit to 0 when the subsystem clock is used and set to 1 when the subsystem clock is not
used.
Be sure to switch CSS from 1 to 0 when bits 1 (MCS) and 0 (MCM0) of the main clock mode register
(MCM) are 1.
Setting is prohibited for the (A1) and (A2) grade products.
X
R
XP
XT
:
:
:
:
CSS
MCC
MCC
FRC
CLS
<7>
0
1
0
1
0
1
0
1
Note 4
After reset: 00H
clock oscillation frequency)
Ring-OSC clock oscillation frequency
Main system clock oscillation frequency (X1 input clock oscillation frequency or Ring-OSC
X1 input clock oscillation frequency
Subsystem clock oscillation frequency
Figure 5-2. Format of Processor Clock Control Register (PCC)
Oscillation possible
Oscillation stopped
On-chip feedback resistor used
On-chip feedback resistor not used
X1 input clock or Ring-OSC clock
Subsystem clock
PCC2
FRC
<6>
Other than above
0
0
0
0
1
0
0
0
0
1
R/W
CHAPTER 5 CLOCK GENERATOR
PCC1
CLS
<5>
Note 1
User’s Manual U16227EJ3V0UD
0
0
1
1
0
0
0
1
1
0
Subsystem clock feedback resistor selection
Control of X1 oscillator operation
PCC0
CSS
<4>
0
1
0
1
0
0
1
0
1
0
Note 3
CPU clock status
f
f
f
f
f
f
Setting prohibited
X
X
X
X
X
XT
/2
/2
/2
/2
/2
2
3
4
3
0
CPU clock (f
PCC2
f
f
Setting prohibited f
Setting prohibited f
Setting prohibited f
R
R
/2
2
MCM0 = 0
Note 5
Note 2
CPU
) selection
PCC1
1
f
f
XP
XP
XP
XP
XP
/2
/2
/2
/2
MCM0 = 1
2
3
4
PCC0
0
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