upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 115

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upd78f0114m6gb-8es

Manufacturer Part Number
upd78f0114m6gb-8es
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown
in Tables 5-3 and 5-4, respectively.
f
R
: Oscillation stopped
A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation
CPU clock: f
f
Notes 1.
XP
: Oscillating
Status 4
2.
3.
4.
5.
XP
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
When “Ring-OSC can be stopped by software” is selected by a mask option, the watchdog timer
stops operating in the HALT and STOP modes, regardless of the source clock of the watchdog timer.
However, oscillation of Ring-OSC does not stop even in the HALT and STOP modes if RSTOP = 0.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
(1) When “Ring-OSC can be stopped by software” is selected by mask option
RSTOP = 1
RSTOP = 0
instruction
Interrupt
HALT
instruction
STOP
Interrupt
Note 1
Figure 5-13. Status Transition Diagram (1/4)
CPU clock: f
f
f
XP
R
: Oscillating
: Oscillating
Status 3
STOP
instruction
(when subsystem clock is not used)
Interrupt
CHAPTER 5 CLOCK GENERATOR
User’s Manual U16227EJ3V0UD
XP
Interrupt
HALT
instruction
MCM0 = 1
MCM0 = 0
STOP
HALT
instruction
Interrupt
Note 4
Note 4
STOP
Note 2
f
CPU clock: f
f
XP
R
Interrupt
: Oscillating
: Oscillating
Status 2
HALT
instruction
HALT instruction
R
instruction
Interrupt
Reset
MSTOP = 1
Reset release
STOP
MSTOP = 0
Note 5
Interrupt
Note 3
f
XP
: Oscillation stopped
CPU clock: f
f
R
: Oscillating
Status 1
R
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