upd78f0114m6gb-8es Renesas Electronics Corporation., upd78f0114m6gb-8es Datasheet - Page 372

• Manufacturer Part Number: upd78f0114m6gb-8es
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

21.4 Operation of Low-Voltage Detector
372
The low-voltage detector can be used in the following two modes.
• Used as reset
• Used as interrupt
The operation is set as follows.
(1) When used as reset
Compares the supply voltage (V
V
Compares the supply voltage (V
when V
DD
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection
<3> Set bit 4 (LVIE) of the low-voltage detection register (LVIM) to 1 (enables reference voltage generator
<4> Use software to instigate a wait of at least 2 ms.
<5> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<6> Use software to instigate a wait of at least 0.2 ms.
<7> Confirm that “supply voltage (V
<8> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V
Figure 21-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers
in this timing chart correspond to <1> to <8> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
• When stopping operation
< V
Either of the following procedures must be executed.
•
•
When using 8-bit memory manipulation instruction:
When using 1-bit memory manipulation instruction:
DD
register (LVIS).
operation).
voltage (V
LVI
Write 00H to LVIM.
Clear LVIMD to 0, LVION to 0, and LVIE to 0 in that order.
.
< V
2. If “POC used” is selected by a mask option, procedures <3> and <4> are not required.
3. If supply voltage (V
LVI
after the processing in <5>.
signal is not generated.
.
LVI
)).
CHAPTER 21 LOW-VOLTAGE DETECTOR
DD
DD
) and detection voltage (V
) and detection voltage (V
DD
DD
) > detection voltage (V
User’s Manual U16227EJ3V0UD
) > detection voltage (V
LVI
LVI
LVI
), and generates an internal reset signal when
LVI
), and generates an interrupt signal (INTLVI)
)” at bit 0 (LVIF) of LVIM.
) when LVIM is set to 1, an internal reset
DD
) < detection