XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 96

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Virtex-II Pro Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
With DCM
Table 44: Global Clock Input to Output Delay for LVCMOS25, 12 mA, Fast Slew Rate,
With DCM
DS083-3 (v2.12) November 11, 2003
Advance Product Specification
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
2. Output timing is measured at 50% V
3. DCM output jitter is already included in the timing calculation.
LVCMOS25 Global Clock Input to Output
Delay using Output Flip-flop, 12 mA, Fast
Slew Rate, with DCM.
For data output with different standards,
adjust the delays with the values shown in
IOB Output Switching Characteristics
Standard
Global Clock and OFF with DCM
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Adjustments, page
R
Description
25.
CC
threshold with test setup shown in
T
Symbol
ICKOFDCM
Virtex-II Pro™ Platform FPGAs: DC and Switching Characteristics
www.xilinx.com
1-800-255-7778
XC2VP100
XC2VP125
XC2VP20
XC2VP30
XC2VP40
XC2VP50
XC2VP70
XC2VP2
XC2VP4
XC2VP7
Device
Figure
6. For other I/O standards, see
-7
Speed Grade
2.40
2.40
2.40
2.40
2.50
2.60
2.70
2.80
-6
2.50
2.60
2.70
2.80
2.90
2.50
2.50
2.50
Table
-5
32.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
39