XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 47

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Functional Description: FPGA
Each global clock multiplexer buffer can be driven either by
the clock pad to distribute a clock directly to the device, or
by the Digital Clock Manager (DCM), discussed in
Clock Manager (DCM), page
Global clock buffers are used to distribute the clock to some
or all synchronous logic elements (such as registers in
CLBs and IOBs, and SelectRAM+ blocks.
Eight global clocks can be used in each quadrant of the
Virtex-II Pro device. Designers should consider the clock
distribution detail of the device prior to pin-locking and floor-
planning. (See the Virtex-II Pro Platform FPGA User
Guide.)
38
NW
SW
Figure 47: Virtex-II Pro Clock Multiplexer Buffer Configuration
40. Each global clock multi-
8 BUFGMUX
16 Clocks
8 BUFGMUX
Clock
Figure 48: Virtex-II Pro Clock Distribution
Pad
NE
SE
Clock Distribution
Clock Multiplexer
Digital
www.xilinx.com
1-800-255-7778
CLKOUT
CLKIN
DCM
Buffer
Clock
Clock
Pad
O
I
NW
SW
plexer buffer can also be driven by local interconnects. The
DCM has clock output(s) that can be connected to global
clock multiplexer buffer inputs, as shown in
Figure 48
In each quadrant, up to eight clocks are organized in clock
rows. A clock row supports up to 16 CLB rows (eight up and
eight down).
To reduce power consumption, any unused clock branches
remain static.
8
8
8 BUFGMUX
8 BUFGMUX
16 Clocks
shows clock distribution in Virtex-II Pro devices.
Interconnect
DS083-2_43_122001
Local
8
8
DS083-2 (v2.9) October 14, 2003
Advance Product Specification
DS083-2_45_122001
8 max
SE
NE
Figure
47.
R