XC2VP70 Xilinx, Inc., XC2VP70 Datasheet - Page 107

• Manufacturer Part Number: XC2VP70
• Description: Virtex-ii Pro Field Programmable Gate Array
• Manufacturer: Xilinx, Inc.

Revision History
Source Synchronous Timing Budgets
This section describes how to use the parameters provided
in the
tion to develop system-specific timing budgets. The follow-
ing analysis provides information necessary for determining
Virtex-II Pro contributions to an overall system timing analy-
sis; no assumptions are made about the effects of
Inter-Symbol Interference or PCB skew.
Virtex-II Pro Transmitter Data-Valid Window (T
T
source-synchronous data bus at the pins of the device and
is calculated as follows:
Notes:
1. Jitter values and accumulation methodology to be provided in
2. This value depends on the clocking methodology used. See
3. This value represents the worst-case clock-tree skew
Revision History
This section records the change history for this module of the data sheet.
50
X
01/31/02
06/17/02
09/03/02
09/27/02
a future release of this document. The absolute period jitter
values found in the
particular DCM output clock used to clock the IOB FF can be
used for a best case analysis.
Note1 for
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
is the minimum aggregate valid data period for a
T
TCKSKEW
Date
X
Source-Synchronous Switching Characteristics
= Data Period - [Jitter
Table 55
(3)
+ TPKGSKEW
Version
1.0
2.0
2.1
2.2
.
DCM Timing Parameters
(1)
•
•
•
•
•
•
•
•
•
Initial Xilinx release.
Added section
+ Duty Cycle Distortion
(4)
Added new Virtex-II Pro family members.
Added timing parameters from speedsfile v1.62.
Added
Added 3.3V-vs-2.5V table entries for some parameters.
Added
Added absolute max ratings for 3.3V-vs-2.5V parameters in
Added recommended operating conditions for V
Updated SSTL2 values in
[Table 32
Added
]
Table
Source-Synchronous Switching Characteristics
Table
section of the
removed in v2.8.]
General Power Supply
37,
10, which contains LVPECL DC specifications.
Pipelined Multiplier Switching
www.xilinx.com
1-800-255-7778
X
(2)
sec-
)
+
Table
4. These values represent the worst-case skew between any two
Virtex-II Pro Receiver Data-Valid Window (R
R
a source-synchronous data bus at the pins of the device
and is calculated as follows:
Notes:
1. This parameter indicates the total sampling error of
2. This value represents the worst-case clock-tree skew
3. These values represent the worst-case skew between any two
X
is the required minimum aggregate valid data period for
6. Added SSTL18 values:
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
Virtex-II Pro DDR input registers across voltage, temperature,
and process. The characterization methodology uses the DCM
to capture the DDR input registers’ edges of operation. These
measurements include:
observable between sequential I/O elements. Significantly
less clock-tree skew exists for I/O registers that are close to
each other and fed by the same or adjacent clock-tree
branches. Use the Xilinx FPGA_Editor and Timing Analyzer
tools to evaluate clock skew specific to your application.
balls of the package: shortest flight time to longest flight time
from Pad to Ball.
R
-
-
-
-
These measurements do not include package or clock tree
skew.
X
Requirements.
= [TSAMP
CLK0 and CLK180 DCM jitter in a quiet system
Worst-case duty-cycle distortion
DCM accuracy (phase offset)
DCM phase shift resolution.
Revision
Characteristics.
(1)
IN
+ TCKSKEW
and RocketIO footnote to
DS083-3 (v2.12) November 11, 2003
section.
Advance Product Specification
Table
Table
(2)
6,
1.
+ TPKGSKEW
Table
31,
Table
Table
X
(3)
)
2.
32.
]
R